📄 jtd.rpt
字号:
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | REDB
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K100QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R R G V G C G G G R V R R R R H G V Y R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E E N C N L N N N E C E E E E O R C E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S S D C D O D D D S C S S S S L E C L S S S S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E E I C E I E E E E D E I L E E E E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R R N K R O R R R T N N O R R R R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V V T V V V V B T W V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E B E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: g:\jtd2\jtd.rpt
jtd
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
D40 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/26( 3%)
D47 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 4/26( 15%)
D51 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/26( 15%)
H6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/26( 11%)
H10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 12/26( 46%)
H15 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 0/2 8/26( 30%)
H16 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/26( 38%)
H17 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 9/26( 34%)
H19 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 11/26( 42%)
H26 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 9/26( 34%)
H28 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
H29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
H33 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 9/26( 34%)
H35 6/ 8( 75%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 10/26( 38%)
H37 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/26( 23%)
H47 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 12/26( 46%)
H50 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 10/26( 38%)
J3 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/26( 7%)
J19 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
J20 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 7/26( 26%)
J21 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 6/26( 23%)
J22 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
J24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/26( 11%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 24/141 ( 17%)
Total logic cells used: 140/4992 ( 2%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.30/4 ( 82%)
Total fan-in: 462/19968 ( 2%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 22
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 140
Total flipflops required: 37
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 19/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 8 0 0 0 8 0 19/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 2 0 0 0 8 0 0 0 0 8 8 8 0 8 0 0 0 0 0 0 8 0 0 8 1 0 0 0 8 0 6 0 2 0 0 0 0 0 0 0 0 0 8 0 0 8 0 0 91/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 3 8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 2 0 0 2 0 0 0 8 0 0 0 0 8 8 8 0 16 8 3 8 0 1 0 8 0 0 8 1 0 0 0 8 0 6 0 2 0 0 3 0 0 0 0 0 0 16 0 0 8 8 0 140/0
Device-Specific Information: g:\jtd2\jtd.rpt
jtd
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 CLOCK
89 - - - 18 INPUT ^ 0 0 0 18 HOLD
88 - - - 19 INPUT ^ 0 0 0 7 RESET
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\jtd2\jtd.rpt
jtd
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
191 - - - 35 OUTPUT 0 1 0 0 A0
192 - - - 37 OUTPUT 0 1 0 0 A1
193 - - - 38 OUTPUT 0 1 0 0 A2
195 - - - 39 OUTPUT 0 0 0 0 A3
179 - - - 25 OUTPUT 0 1 0 0 B0
187 - - - 28 OUTPUT 0 1 0 0 B1
189 - - - 30 OUTPUT 0 1 0 0 B2
190 - - - 33 OUTPUT 0 1 0 0 B3
174 - - - 22 OUTPUT 0 1 0 0 C0
175 - - - 22 OUTPUT 0 1 0 0 C1
176 - - - 23 OUTPUT 0 1 0 0 C2
177 - - - 24 OUTPUT 0 0 0 0 C3
169 - - - 18 OUTPUT 0 1 0 0 D0
170 - - - 19 OUTPUT 0 1 0 0 D1
172 - - - 20 OUTPUT 0 1 0 0 D2
173 - - - 21 OUTPUT 0 1 0 0 D3
205 - - - 50 OUTPUT 0 1 0 0 GREENA
90 - - - 16 OUTPUT 0 1 0 0 GREENB
202 - - - 47 OUTPUT 0 1 0 0 REDA
135 - - D -- OUTPUT 0 1 0 0 REDB
203 - - - 48 OUTPUT 0 1 0 0 YELLOWA
92 - - - 15 OUTPUT 0 1 0 0 YELLOWB
Code:
s = Synthesized pin or logic cell
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