jtd.rpt

在maxplus2环境下的vhdl设计交通灯

Project Information                                            g:\jtd2\jtd.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/06/2009 19:23:23

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

jtd       EP1K100QC208-3   3      22     0    0         0  %    140      2  %

User Pins:                 3      22     0  



Project Information                                            g:\jtd2\jtd.rpt

** PROJECT TIMING MESSAGES **

Warning: Timing characteristics of device EP1K100QC208-3 are preliminary


Project Information                                            g:\jtd2\jtd.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

jtd@191                           A0
jtd@192                           A1
jtd@193                           A2
jtd@195                           A3
jtd@179                           B0
jtd@187                           B1
jtd@189                           B2
jtd@190                           B3
jtd@79                            CLOCK
jtd@174                           C0
jtd@175                           C1
jtd@176                           C2
jtd@177                           C3
jtd@169                           D0
jtd@170                           D1
jtd@172                           D2
jtd@173                           D3
jtd@205                           GREENA
jtd@90                            GREENB
jtd@89                            HOLD
jtd@202                           REDA
jtd@135                           REDB
jtd@88                            RESET
jtd@203                           YELLOWA
jtd@92                            YELLOWB


Project Information                                            g:\jtd2\jtd.rpt

** FILE HIERARCHY **



|counter:27|
|counter:27|lpm_add_sub:160|
|counter:27|lpm_add_sub:160|addcore:adder|
|counter:27|lpm_add_sub:160|altshift:result_ext_latency_ffs|
|counter:27|lpm_add_sub:160|altshift:carry_ext_latency_ffs|
|counter:27|lpm_add_sub:160|altshift:oflow_ext_latency_ffs|
|fredevider:5|
|fredevider:5|lpm_add_sub:121|
|fredevider:5|lpm_add_sub:121|addcore:adder|
|fredevider:5|lpm_add_sub:121|altshift:result_ext_latency_ffs|
|fredevider:5|lpm_add_sub:121|altshift:carry_ext_latency_ffs|
|fredevider:5|lpm_add_sub:121|altshift:oflow_ext_latency_ffs|
|countroller:26|
|countroller:26|lpm_add_sub:272|
|countroller:26|lpm_add_sub:272|addcore:adder|
|countroller:26|lpm_add_sub:272|altshift:result_ext_latency_ffs|
|countroller:26|lpm_add_sub:272|altshift:carry_ext_latency_ffs|
|countroller:26|lpm_add_sub:272|altshift:oflow_ext_latency_ffs|
|countroller:26|lpm_add_sub:329|
|countroller:26|lpm_add_sub:329|addcore:adder|
|countroller:26|lpm_add_sub:329|altshift:result_ext_latency_ffs|
|countroller:26|lpm_add_sub:329|altshift:carry_ext_latency_ffs|
|countroller:26|lpm_add_sub:329|altshift:oflow_ext_latency_ffs|
|countroller:26|lpm_add_sub:386|
|countroller:26|lpm_add_sub:386|addcore:adder|
|countroller:26|lpm_add_sub:386|altshift:result_ext_latency_ffs|
|countroller:26|lpm_add_sub:386|altshift:carry_ext_latency_ffs|
|countroller:26|lpm_add_sub:386|altshift:oflow_ext_latency_ffs|
|countroller:26|lpm_add_sub:691|
|countroller:26|lpm_add_sub:691|addcore:adder|
|countroller:26|lpm_add_sub:691|altshift:result_ext_latency_ffs|
|countroller:26|lpm_add_sub:691|altshift:carry_ext_latency_ffs|
|countroller:26|lpm_add_sub:691|altshift:oflow_ext_latency_ffs|
|countroller:26|lpm_add_sub:748|
|countroller:26|lpm_add_sub:748|addcore:adder|
|countroller:26|lpm_add_sub:748|altshift:result_ext_latency_ffs|
|countroller:26|lpm_add_sub:748|altshift:carry_ext_latency_ffs|
|countroller:26|lpm_add_sub:748|altshift:oflow_ext_latency_ffs|
|countroller:26|lpm_add_sub:805|
|countroller:26|lpm_add_sub:805|addcore:adder|
|countroller:26|lpm_add_sub:805|altshift:result_ext_latency_ffs|
|countroller:26|lpm_add_sub:805|altshift:carry_ext_latency_ffs|
|countroller:26|lpm_add_sub:805|altshift:oflow_ext_latency_ffs|
|fenwei:24|
|fenwei:24|lpm_add_sub:390|
|fenwei:24|lpm_add_sub:390|addcore:adder|
|fenwei:24|lpm_add_sub:390|altshift:result_ext_latency_ffs|
|fenwei:24|lpm_add_sub:390|altshift:carry_ext_latency_ffs|
|fenwei:24|lpm_add_sub:390|altshift:oflow_ext_latency_ffs|
|fenwei:24|lpm_add_sub:437|
|fenwei:24|lpm_add_sub:437|addcore:adder|
|fenwei:24|lpm_add_sub:437|altshift:result_ext_latency_ffs|
|fenwei:24|lpm_add_sub:437|altshift:carry_ext_latency_ffs|
|fenwei:24|lpm_add_sub:437|altshift:oflow_ext_latency_ffs|
|fenwei:24|lpm_add_sub:484|
|fenwei:24|lpm_add_sub:484|addcore:adder|
|fenwei:24|lpm_add_sub:484|altshift:result_ext_latency_ffs|
|fenwei:24|lpm_add_sub:484|altshift:carry_ext_latency_ffs|
|fenwei:24|lpm_add_sub:484|altshift:oflow_ext_latency_ffs|
|fenwei:24|lpm_add_sub:531|
|fenwei:24|lpm_add_sub:531|addcore:adder|
|fenwei:24|lpm_add_sub:531|altshift:result_ext_latency_ffs|
|fenwei:24|lpm_add_sub:531|altshift:carry_ext_latency_ffs|
|fenwei:24|lpm_add_sub:531|altshift:oflow_ext_latency_ffs|
|fenwei:24|lpm_add_sub:578|
|fenwei:24|lpm_add_sub:578|addcore:adder|
|fenwei:24|lpm_add_sub:578|altshift:result_ext_latency_ffs|
|fenwei:24|lpm_add_sub:578|altshift:carry_ext_latency_ffs|
|fenwei:24|lpm_add_sub:578|altshift:oflow_ext_latency_ffs|
|fenwei:24|lpm_add_sub:625|
|fenwei:24|lpm_add_sub:625|addcore:adder|
|fenwei:24|lpm_add_sub:625|altshift:result_ext_latency_ffs|
|fenwei:24|lpm_add_sub:625|altshift:carry_ext_latency_ffs|
|fenwei:24|lpm_add_sub:625|altshift:oflow_ext_latency_ffs|
|fenwei2:25|
|fenwei2:25|lpm_add_sub:390|
|fenwei2:25|lpm_add_sub:390|addcore:adder|
|fenwei2:25|lpm_add_sub:390|altshift:result_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:390|altshift:carry_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:390|altshift:oflow_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:437|
|fenwei2:25|lpm_add_sub:437|addcore:adder|
|fenwei2:25|lpm_add_sub:437|altshift:result_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:437|altshift:carry_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:437|altshift:oflow_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:484|
|fenwei2:25|lpm_add_sub:484|addcore:adder|
|fenwei2:25|lpm_add_sub:484|altshift:result_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:484|altshift:carry_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:484|altshift:oflow_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:531|
|fenwei2:25|lpm_add_sub:531|addcore:adder|
|fenwei2:25|lpm_add_sub:531|altshift:result_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:531|altshift:carry_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:531|altshift:oflow_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:578|
|fenwei2:25|lpm_add_sub:578|addcore:adder|
|fenwei2:25|lpm_add_sub:578|altshift:result_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:578|altshift:carry_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:578|altshift:oflow_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:625|
|fenwei2:25|lpm_add_sub:625|addcore:adder|
|fenwei2:25|lpm_add_sub:625|altshift:result_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:625|altshift:carry_ext_latency_ffs|
|fenwei2:25|lpm_add_sub:625|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                                   g:\jtd2\jtd.rpt
jtd

***** Logic for device 'jtd' compiled without errors.




Device: EP1K100QC208-3

ACEX 1K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF

                                                                                                                         
                                                                                                                         
                R R R   R       R R R R R                   R           R                       R R R   R R R R R R R R  
                E E E   E Y     E E E E E                   E           E                       E E E   E E E E E E E E  
                S S S G S E   V S S S S S                   S V         S                       S S S   S S S S S S S S  
                E E E R E L   C E E E E E   V               E C         E   V                   E E E V E E E E E E E E  
                R R R E R L R C R R R R R   C               R C         R   C                   R R R C R R R R R R R R  
                V V V E V O E I V V V V V   C           G   V I G G G G V   C             G     V V V C V V V V V V V V  
                E E E N E W D N E E E E E A I A A A B B N B E N N N N N E B I C C C C D D N D D E E E I E E E E E E E E  
                D D D A D A A T D D D D D 3 O 2 1 0 3 2 D 1 D T D D D D D 0 O 3 2 1 0 3 2 D 1 0 D D D O D D D D D D D D  
              ----------------------------------------------------------------------------------------------------------_ 
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