c8051f320.h

基于c8051f320单片机开发的实验例程

//-----------------------------------------------------------------------------
// C8051F320.h
//-----------------------------------------------------------------------------
// Copyright 2005 Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F32x family.
//
//
// FID:            32X000008
// Target:         C8051F320, 'F321
// Tool chain:     Keil
// Command Line:   None
//
// Release 2.1
//    -All changes by GRP
//    -09 DEC 2005
//    -added EMI0CN
//
// Release 2.0
//    -All changes by PKC
//    -09 NOV 2005
//    -Converted file to new coding guidelines
//    -Added #defines for interrupt priorities
//    -Added #ifndef/#define to allow multiple includes of file
//
// Release 1.5
//    -Latest release before new firmware coding standard
//

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#ifndef C8051F320_H
#define C8051F320_H

//-----------------------------------------------------------------------------
// Byte Registers
//-----------------------------------------------------------------------------

sfr P0       = 0x80;                   // Port0
sfr SP       = 0x81;                   // Stack pointer
sfr DPL      = 0x82;                   // Data pointer - Low byte
sfr DPH      = 0x83;                   // Data pointer - High byte
sfr PCON     = 0x87;                   // Power control register
sfr TCON     = 0x88;                   // Timer control register
sfr TMOD     = 0x89;                   // Timer mode register
sfr TL0      = 0x8A;                   // Timer0 - Low byte
sfr TL1      = 0x8B;                   // Timer1 - Low byte
sfr TH0      = 0x8C;                   // Timer0 - High byte
sfr TH1      = 0x8D;                   // Timer1 - High byte
sfr CKCON    = 0x8E;                   // Clock control register
sfr PSCTL    = 0x8F;                   // Program store r/w control
sfr P1       = 0x90;                   // Port1
sfr TMR3CN   = 0x91;                   // Timer3 control register
sfr TMR3RLL  = 0x92;                   // Timer3 reload register - Low byte
sfr TMR3RLH  = 0x93;                   // Timer3 reload register - High byte
sfr TMR3L    = 0x94;                   // Timer3 - Low byte
sfr TMR3H    = 0x95;                   // Timer3 - High byte
sfr USB0ADR  = 0x96;                   // USB0 address port
sfr USB0DAT  = 0x97;                   // USB0 data port
sfr SCON0    = 0x98;                   // UART0 control register
sfr SBUF0    = 0x99;                   // UART0 data buffer register
sfr CPT1CN   = 0x9A;                   // Comparator1 control register
sfr CPT0CN   = 0x9B;                   // Comparator0 control register
sfr CPT1MD   = 0x9C;                   // Comparator1 mode selection register
sfr CPT0MD   = 0x9D;                   // Comparator0 mode selection register
sfr CPT1MX   = 0x9E;                   // Comparator1 mux selection register
sfr CPT0MX   = 0x9F;                   // Comparator0 mux selection register
sfr P2       = 0xA0;                   // Port2
sfr SPICFG   = 0xA1;                   // SPI0 configuration register
sfr SPI0CFG  = 0xA1;                   // SPI0 configuration register
sfr SPICKR   = 0xA2;                   // SPI0 clock configuration register
sfr SPI0CKR  = 0xA2;                   // SPI0 clock configuration register
sfr SPIDAT   = 0xA3;                   // SPI0 data register
sfr SPI0DAT  = 0xA3;                   // SPI0 data register
sfr P0MDOUT  = 0xA4;                   // Port0 output mode register
sfr P1MDOUT  = 0xA5;                   // Port1 output mode register
sfr P2MDOUT  = 0xA6;                   // Port2 output mode register
sfr P3MDOUT  = 0xA7;                   // Port3 output mode register
sfr IE       = 0xA8;                   // Interrupt enable
sfr CLKSEL   = 0xA9;                   // Clock source select
sfr EMI0CN   = 0xAA;                   // External Memory Interface Control
sfr P3       = 0xB0;                   // Port3
sfr OSCXCN   = 0xB1;                   // External oscillator control
sfr OSCICN   = 0xB2;                   // Internal oscillator control
sfr OSCICL   = 0xB3;                   // Internal oscillator calibration
sfr FLSCL    = 0xB6;                   // Flash scale register
sfr FLKEY    = 0xB7;                   // Flash lock & key register
sfr IP       = 0xB8;                   // Interrupt priority
sfr CLKMUL   = 0xB9;                   // Clock multiplier control register
sfr AMX0N    = 0xBA;                   // ADC0 mux negative channel selection
sfr AMX0P    = 0xBB;                   // ADC0 mux positive channel selection
sfr ADC0CF   = 0xBC;                   // ADC0 configuration
sfr ADC0L    = 0xBD;                   // ADC0 data low
sfr ADC0H    = 0xBE;                   // ADC0 data high
sfr SMB0CN   = 0xC0;                   // SMBus control
sfr SMB0CF   = 0xC1;                   // SMBus configuration
sfr SMB0DAT  = 0xC2;                   // SMBus data
sfr ADC0GTL  = 0xC3;                   // ADC0 greater-than data low register
sfr ADC0GTH  = 0xC4;                   // ADC0 greater-than data high register
sfr ADC0LTL  = 0xC5;                   // ADC0 less-than data low register
sfr ADC0LTH  = 0xC6;                   // ADC0 less-than data high register
sfr TMR2CN   = 0xC8;                   // Timer2 control register
sfr REG0CN   = 0xC9;                   // Regulator control register
sfr TMR2RLL  = 0xCA;                   // Timer2 reload register - Low byte
sfr TMR2RLH  = 0xCB;                   // Timer2 reload register - High byte
sfr TMR2L    = 0xCC;                   // Timer2 - Low byte
sfr TMR2H    = 0xCD;                   // Timer2 - High byte
sfr PSW      = 0xD0;                   // Program Status Word
sfr REF0CN   = 0xD1;                   // Voltage reference control register
sfr P0SKIP   = 0xD4;                   // Port0 crossbar skip register
sfr P1SKIP   = 0xD5;                   // Port1 crossbar skip register
sfr P2SKIP   = 0xD6;                   // Port2 crossbar skip register
sfr USB0XCN  = 0xD7;                   // USB0 tranceiver control register
sfr PCA0CN   = 0xD8;                   // PCA0 control register
sfr PCA0MD   = 0xD9;                   // PCA0 mode register
sfr PCA0CPM0 = 0xDA;                   // Capture/compare module0 mode
sfr PCA0CPM1 = 0xDB;                   // Capture/compare module1 mode
sfr PCA0CPM2 = 0xDC;                   // Capture/compare module2 mode
sfr PCA0CPM3 = 0xDD;                   // Capture/compare module3 mode
sfr PCA0CPM4 = 0xDE;                   // Capture/compare module4 mode
sfr ACC      = 0xE0;                   // Accumulator
sfr XBR0     = 0xE1;                   // Port I/O crossbar register 0
sfr XBR1     = 0xE2;                   // Port I/O crossbar register 1
sfr IT01CF   = 0xE4;                   // Int0/int1 configuration register
sfr EIE1     = 0xE6;                   // Extended interrupt enable 1
sfr EIE2     = 0xE7;                   // Extended interrupt enable 2
sfr ADC0CN   = 0xE8;                   // ADC0 control register
sfr PCA0CPL1 = 0xE9;                   // Capture/compare module1 - Low byte
sfr PCA0CPH1 = 0xEA;                   // Capture/compare module1 - High byte
sfr PCA0CPL2 = 0xEB;                   // Capture/compare module2 - Low byte
sfr PCA0CPH2 = 0xEC;                   // Capture/compare module2 - High byte
sfr PCA0CPL3 = 0xED;                   // Capture/compare module3 - Low byte
sfr PCA0CPH3 = 0xEE;                   // Capture/compare module3 - High byte
sfr RSTSRC   = 0xEF;                   // Reset source register
sfr B        = 0xF0;                   // B register
sfr P0MDIN   = 0xF1;                   // Port0 input mode register
sfr P1MDIN   = 0xF2;                   // Port1 input mode register
sfr P2MDIN   = 0xF3;                   // Port2 input mode register
sfr P3MDIN   = 0xF4;                   // Port3 input mode register
sfr EIP1     = 0xF6;                   // Extended interrupt priority 1