pl_fsk.fit.eqn

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

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--B1_y is PL_FSK1:inst|y at LC_X1_Y17_N5
--operation mode is normal

B1_y_lut_out = x & B1_f2 # !x & (B1_f1);
B1_y = DFFEAS(B1_y_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_f2 is PL_FSK1:inst|f2 at LC_X1_Y17_N9
--operation mode is normal

B1_f2_lut_out = !C1_q1[0];
B1_f2 = DFFEAS(B1_f2_lut_out, GLOBAL(clk), VCC, , start, , , , );


--B1_f1 is PL_FSK1:inst|f1 at LC_X1_Y17_N7
--operation mode is normal

B1_f1_lut_out = A1L5 # !A1L4 & B1_f1;
B1_f1 = DFFEAS(B1_f1_lut_out, GLOBAL(clk), VCC, , start, , , , );


--C1_m[2] is PL_FSK2:inst5|m[2] at LC_X2_Y17_N0
--operation mode is normal

C1_m[2]_lut_out = C1_m[2] $ (!A1L3 & C1_m[0] & C1_m[1]);
C1_m[2] = DFFEAS(C1_m[2]_lut_out, GLOBAL(C1_xx), !GLOBAL(A1L4), , , , , , );


--C1_q1[3] is PL_FSK2:inst5|q1[3] at LC_X2_Y17_N6
--operation mode is normal

C1_q1[3]_lut_out = !A1L4 & start & (C1L1 $ C1_q1[3]);
C1_q1[3] = DFFEAS(C1_q1[3]_lut_out, GLOBAL(clk), VCC, , , , , , );


--C1_q1[1] is PL_FSK2:inst5|q1[1] at LC_X2_Y17_N8
--operation mode is normal

C1_q1[1]_lut_out = !A1L4 & start & (C1_q1[1] $ C1_q1[0]);
C1_q1[1] = DFFEAS(C1_q1[1]_lut_out, GLOBAL(clk), VCC, , , , , , );


--C1_q1[0] is PL_FSK2:inst5|q1[0] at LC_X2_Y17_N7
--operation mode is normal

C1_q1[0]_lut_out = start & !C1_q1[0];
C1_q1[0] = DFFEAS(C1_q1[0]_lut_out, GLOBAL(clk), VCC, , , , , , );


--C1_q1[2] is PL_FSK2:inst5|q1[2] at LC_X2_Y17_N1
--operation mode is normal

C1_q1[2]_lut_out = !A1L4 & start & (C1_q1[2] $ C1L2);
C1_q1[2] = DFFEAS(C1_q1[2]_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L3 is rtl~0 at LC_X2_Y17_N2
--operation mode is normal

A1L3 = !C1_q1[0] & C1_q1[3] & !C1_q1[2] & C1_q1[1];


--A1L5 is rtl~53 at LC_X1_Y17_N6
--operation mode is normal

A1L5 = C1_q1[2] & C1_q1[0] & !C1_q1[1] & !C1_q1[3];


--A1L4 is rtl~2 at LC_X2_Y17_N9
--operation mode is normal

A1L4 = C1_q1[3] & C1_q1[0] & !C1_q1[2] & C1_q1[1];


--C1_m[1] is PL_FSK2:inst5|m[1] at LC_X2_Y17_N4
--operation mode is normal

C1_m[1]_lut_out = C1_m[1] $ (!A1L3 & C1_m[0]);
C1_m[1] = DFFEAS(C1_m[1]_lut_out, GLOBAL(C1_xx), !GLOBAL(A1L4), , , , , , );


--C1_m[0] is PL_FSK2:inst5|m[0] at LC_X2_Y17_N5
--operation mode is normal

C1_m[0]_lut_out = C1_m[0] $ !A1L3;
C1_m[0] = DFFEAS(C1_m[0]_lut_out, GLOBAL(C1_xx), !GLOBAL(A1L4), , , , , , );


--C1_xx is PL_FSK2:inst5|xx at LC_X1_Y17_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_xx_lut_out = GND;
C1_xx = DFFEAS(C1_xx_lut_out, GLOBAL(clk), VCC, , , B1_y, , , VCC);


--C1L1 is PL_FSK2:inst5|add~142 at LC_X1_Y17_N2
--operation mode is normal

C1L1 = C1_q1[1] & C1_q1[0] & (C1_q1[2]);


--C1L2 is PL_FSK2:inst5|add~143 at LC_X1_Y17_N4
--operation mode is normal

C1L2 = C1_q1[0] & (C1_q1[1]);


--C1_y is PL_FSK2:inst5|y at LC_X2_Y17_N3
--operation mode is normal

C1_y = A1L3 & C1_m[2] # !A1L3 & (C1_y);


--x is x at PIN_L21
--operation mode is input

x = INPUT();


--clk is clk at PIN_L2
--operation mode is input

clk = INPUT();


--start is start at PIN_M20
--operation mode is input

start = INPUT();


--c is c at PIN_N20
--operation mode is output

c = OUTPUT(B1_y);


--y is y at PIN_N21
--operation mode is output

y = OUTPUT(C1_y);