pl_fsk.map.rpt

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+


+-------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                       ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 17                  ;
;     -- Combinational with no register       ; 6                   ;
;     -- Register only                        ; 1                   ;
;     -- Combinational with a register        ; 10                  ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 7                   ;
;     -- 3 input functions                    ; 5                   ;
;     -- 2 input functions                    ; 3                   ;
;     -- 1 input functions                    ; 1                   ;
;     -- 0 input functions                    ; 0                   ;
;         -- Combinational cells for routing  ; 0                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 17                  ;
;     -- arithmetic mode                      ; 0                   ;
;     -- qfbk mode                            ; 0                   ;
;     -- register cascade mode                ; 0                   ;
;     -- synchronous clear/load mode          ; 0                   ;
;     -- asynchronous clear/load mode         ; 3                   ;
;                                             ;                     ;
; Total registers                             ; 11                  ;
; I/O pins                                    ; 5                   ;
; Maximum fan-out node                        ; PL_FSK2:inst5|q1[0] ;
; Maximum fan-out                             ; 8                   ;
; Total fan-out                               ; 69                  ;
; Average fan-out                             ; 3.14                ;
+---------------------------------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name   ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
; |PL_FSK                    ; 17 (3)      ; 11           ; 0           ; 0            ; 0       ; 0         ; 0         ; 5    ; 0            ; 6 (3)        ; 1 (0)             ; 10 (0)           ; 0 (0)           ; 0 (0)      ; |PL_FSK               ;
;    |PL_FSK1:inst|          ; 3 (3)       ; 3            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |PL_FSK|PL_FSK1:inst  ;
;    |PL_FSK2:inst5|         ; 11 (11)     ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 1 (1)             ; 7 (7)            ; 0 (0)           ; 0 (0)      ; |PL_FSK|PL_FSK2:inst5 ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; PL_FSK2:inst5|y                               ;   ;
; Number of user-specified and inferred latches ; 1 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 11    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 3     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |PL_FSK|PL_FSK2:inst5|q1[3] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |PL_FSK|PL_FSK1:inst|q1[3]  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Sat Mar 18 11:18:23 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PL_FSK -c PL_FSK
Info: Found 2 design units, including 1 entities, in source file PL_FSK2.vhd
    Info: Found design unit 1: PL_FSK2-behv
    Info: Found entity 1: PL_FSK2
Info: Found 2 design units, including 1 entities, in source file PL_FSK1.vhd
    Info: Found design unit 1: PL_FSK1-behv
    Info: Found entity 1: PL_FSK1
Info: Found 1 design units, including 1 entities, in source file PL_FSK.bdf
    Info: Found entity 1: PL_FSK
Info: Elaborating entity "PL_FSK" for the top level hierarchy
Info: Elaborating entity "PL_FSK1" for hierarchy "PL_FSK1:inst"
Info: Elaborating entity "PL_FSK2" for hierarchy "PL_FSK2:inst5"
Warning (10492): VHDL Process Statement warning at PL_FSK2.vhd(40): signal "m" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at PL_FSK2.vhd(35): signal or variable "y" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "y" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Duplicate registers merged to single register
    Info: Duplicate register "PL_FSK1:inst|q1[3]" merged to single register "PL_FSK2:inst5|q1[3]"
    Info: Duplicate register "PL_FSK1:inst|q1[2]" merged to single register "PL_FSK2:inst5|q1[2]"
    Info: Duplicate register "PL_FSK1:inst|q1[1]" merged to single register "PL_FSK2:inst5|q1[1]"
    Info: Duplicate register "PL_FSK1:inst|q1[0]" merged to single register "PL_FSK2:inst5|q1[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "PL_FSK1:inst|q2" merged to single register "PL_FSK2:inst5|q1[0]"
Info: Implemented 22 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 2 output pins
    Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Mar 18 11:18:32 2006
    Info: Elapsed time: 00:00:10