pl_fsk.qsf

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

# Copyright (C) 1991-2005 Altera Corporation
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# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
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# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# applicable agreement for further details.


# The default values for assignments are stored in the file
#		PL_FSK_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Stratix
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY PL_FSK
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:57:31  MARCH 17, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name VHDL_FILE PL_FSK2.vhd
set_global_assignment -name VHDL_FILE PL_FSK1.vhd
set_global_assignment -name BDF_FILE PL_FSK.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE PL_FSK.vwf