pl_fsk.map.qmsg

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 18 11:18:23 2006 " "Info: Processing started: Sat Mar 18 11:18:23 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PL_FSK -c PL_FSK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PL_FSK -c PL_FSK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PL_FSK2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PL_FSK2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PL_FSK2-behv " "Info: Found design unit 1: PL_FSK2-behv" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PL_FSK2 " "Info: Found entity 1: PL_FSK2" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PL_FSK1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PL_FSK1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PL_FSK1-behv " "Info: Found design unit 1: PL_FSK1-behv" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PL_FSK1 " "Info: Found entity 1: PL_FSK1" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PL_FSK.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PL_FSK.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PL_FSK " "Info: Found entity 1: PL_FSK" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PL_FSK " "Info: Elaborating entity \"PL_FSK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PL_FSK1 PL_FSK1:inst " "Info: Elaborating entity \"PL_FSK1\" for hierarchy \"PL_FSK1:inst\"" {  } { { "PL_FSK.bdf" "inst" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 48 352 448 144 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PL_FSK2 PL_FSK2:inst5 " "Info: Elaborating entity \"PL_FSK2\" for hierarchy \"PL_FSK2:inst5\"" {  } { { "PL_FSK.bdf" "inst5" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 192 512 608 288 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "m PL_FSK2.vhd(40) " "Warning (10492): VHDL Process Statement warning at PL_FSK2.vhd(40): signal \"m\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y PL_FSK2.vhd(35) " "Warning (10631): VHDL Process Statement warning at PL_FSK2.vhd(35): signal or variable \"y\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"y\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 35 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "PL_FSK1:inst\|q1\[3\] PL_FSK2:inst5\|q1\[3\] " "Info: Duplicate register \"PL_FSK1:inst\|q1\[3\]\" merged to single register \"PL_FSK2:inst5\|q1\[3\]\"" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "PL_FSK1:inst\|q1\[2\] PL_FSK2:inst5\|q1\[2\] " "Info: Duplicate register \"PL_FSK1:inst\|q1\[2\]\" merged to single register \"PL_FSK2:inst5\|q1\[2\]\"" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "PL_FSK1:inst\|q1\[1\] PL_FSK2:inst5\|q1\[1\] " "Info: Duplicate register \"PL_FSK1:inst\|q1\[1\]\" merged to single register \"PL_FSK2:inst5\|q1\[1\]\"" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "PL_FSK1:inst\|q1\[0\] PL_FSK2:inst5\|q1\[0\] " "Info: Duplicate register \"PL_FSK1:inst\|q1\[0\]\" merged to single register \"PL_FSK2:inst5\|q1\[0\]\"" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "PL_FSK1:inst\|q2 PL_FSK2:inst5\|q1\[0\] " "Info: Duplicate register \"PL_FSK1:inst\|q2\" merged to single register \"PL_FSK2:inst5\|q1\[0\]\"" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "22 " "Info: Implemented 22 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 18 11:18:32 2006 " "Info: Processing ended: Sat Mar 18 11:18:32 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}