pl_fsk.tan.qmsg

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "PL_FSK2:inst5\|q1\[1\] PL_FSK2:inst5\|m\[0\] clk 2.4 ns " "Info: Found hold time violation between source  pin or register \"PL_FSK2:inst5\|q1\[1\]\" and destination pin or register \"PL_FSK2:inst5\|m\[0\]\" for clock \"clk\" (Hold time is 2.4 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.546 ns + Largest " "Info: + Largest clock skew is 3.546 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.474 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.698 ns) 3.084 ns PL_FSK2:inst5\|xx 2 REG LC_X1_Y17_N8 3 " "Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X1_Y17_N8; Fanout = 3; REG Node = 'PL_FSK2:inst5\|xx'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.359 ns" { clk PL_FSK2:inst5|xx } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.848 ns) + CELL(0.542 ns) 6.474 ns PL_FSK2:inst5\|m\[0\] 3 REG LC_X2_Y17_N5 3 " "Info: 3: + IC(2.848 ns) + CELL(0.542 ns) = 6.474 ns; Loc. = LC_X2_Y17_N5; Fanout = 3; REG Node = 'PL_FSK2:inst5\|m\[0\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "3.390 ns" { PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.965 ns ( 30.35 % ) " "Info: Total cell delay = 1.965 ns ( 30.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.509 ns ( 69.65 % ) " "Info: Total interconnect delay = 4.509 ns ( 69.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "6.474 ns" { clk PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "6.474 ns" { clk clk~out0 PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } { 0.000ns 0.000ns 1.661ns 2.848ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.928 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.542 ns) 2.928 ns PL_FSK2:inst5\|q1\[1\] 2 REG LC_X2_Y17_N8 6 " "Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X2_Y17_N8; Fanout = 6; REG Node = 'PL_FSK2:inst5\|q1\[1\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.203 ns" { clk PL_FSK2:inst5|q1[1] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.27 % ) " "Info: Total cell delay = 1.267 ns ( 43.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.661 ns ( 56.73 % ) " "Info: Total interconnect delay = 1.661 ns ( 56.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK2:inst5|q1[1] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK2:inst5|q1[1] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "6.474 ns" { clk PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "6.474 ns" { clk clk~out0 PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } { 0.000ns 0.000ns 1.661ns 2.848ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK2:inst5|q1[1] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK2:inst5|q1[1] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.090 ns - Shortest register register " "Info: - Shortest register to register delay is 1.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PL_FSK2:inst5\|q1\[1\] 1 REG LC_X2_Y17_N8 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N8; Fanout = 6; REG Node = 'PL_FSK2:inst5\|q1\[1\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { PL_FSK2:inst5|q1[1] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.075 ns) 0.507 ns rtl~0 2 COMB LC_X2_Y17_N2 4 " "Info: 2: + IC(0.432 ns) + CELL(0.075 ns) = 0.507 ns; Loc. = LC_X2_Y17_N2; Fanout = 4; COMB Node = 'rtl~0'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.507 ns" { PL_FSK2:inst5|q1[1] rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.223 ns) 1.090 ns PL_FSK2:inst5\|m\[0\] 3 REG LC_X2_Y17_N5 3 " "Info: 3: + IC(0.360 ns) + CELL(0.223 ns) = 1.090 ns; Loc. = LC_X2_Y17_N5; Fanout = 3; REG Node = 'PL_FSK2:inst5\|m\[0\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.583 ns" { rtl~0 PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.298 ns ( 27.34 % ) " "Info: Total cell delay = 0.298 ns ( 27.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns ( 72.66 % ) " "Info: Total interconnect delay = 0.792 ns ( 72.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "1.090 ns" { PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "1.090 ns" { PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|m[0] } { 0.000ns 0.432ns 0.360ns } { 0.000ns 0.075ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "6.474 ns" { clk PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "6.474 ns" { clk clk~out0 PL_FSK2:inst5|xx PL_FSK2:inst5|m[0] } { 0.000ns 0.000ns 1.661ns 2.848ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK2:inst5|q1[1] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK2:inst5|q1[1] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "1.090 ns" { PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|m[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "1.090 ns" { PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|m[0] } { 0.000ns 0.432ns 0.360ns } { 0.000ns 0.075ns 0.223ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "PL_FSK2:inst5\|q1\[0\] start clk 2.405 ns register " "Info: tsu for register \"PL_FSK2:inst5\|q1\[0\]\" (data pin = \"start\", clock pin = \"clk\") is 2.405 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.323 ns + Longest pin register " "Info: + Longest pin to register delay is 5.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns start 1 PIN PIN_M20 6 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 6; PIN Node = 'start'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { start } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 56 104 272 72 "start" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.037 ns) + CELL(0.458 ns) 5.323 ns PL_FSK2:inst5\|q1\[0\] 2 REG LC_X2_Y17_N7 8 " "Info: 2: + IC(4.037 ns) + CELL(0.458 ns) = 5.323 ns; Loc. = LC_X2_Y17_N7; Fanout = 8; REG Node = 'PL_FSK2:inst5\|q1\[0\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.495 ns" { start PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.286 ns ( 24.16 % ) " "Info: Total cell delay = 1.286 ns ( 24.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.037 ns ( 75.84 % ) " "Info: Total interconnect delay = 4.037 ns ( 75.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "5.323 ns" { start PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "5.323 ns" { start start~out0 PL_FSK2:inst5|q1[0] } { 0.000ns 0.000ns 4.037ns } { 0.000ns 0.828ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.928 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.542 ns) 2.928 ns PL_FSK2:inst5\|q1\[0\] 2 REG LC_X2_Y17_N7 8 " "Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X2_Y17_N7; Fanout = 8; REG Node = 'PL_FSK2:inst5\|q1\[0\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.203 ns" { clk PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.27 % ) " "Info: Total cell delay = 1.267 ns ( 43.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.661 ns ( 56.73 % ) " "Info: Total interconnect delay = 1.661 ns ( 56.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK2:inst5|q1[0] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "5.323 ns" { start PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "5.323 ns" { start start~out0 PL_FSK2:inst5|q1[0] } { 0.000ns 0.000ns 4.037ns } { 0.000ns 0.828ns 0.458ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK2:inst5|q1[0] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y PL_FSK2:inst5\|y 8.158 ns register " "Info: tco from clock \"clk\" to destination pin \"y\" through register \"PL_FSK2:inst5\|y\" is 8.158 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.059 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.698 ns) 3.084 ns PL_FSK2:inst5\|q1\[0\] 2 REG LC_X2_Y17_N7 8 " "Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X2_Y17_N7; Fanout = 8; REG Node = 'PL_FSK2:inst5\|q1\[0\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.359 ns" { clk PL_FSK2:inst5|q1[0] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.366 ns) 3.850 ns rtl~0 3 COMB LC_X2_Y17_N2 4 " "Info: 3: + IC(0.400 ns) + CELL(0.366 ns) = 3.850 ns; Loc. = LC_X2_Y17_N2; Fanout = 4; COMB Node = 'rtl~0'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.766 ns" { PL_FSK2:inst5|q1[0] rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 4.059 ns PL_FSK2:inst5\|y 4 REG LC_X2_Y17_N3 1 " "Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 4.059 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5\|y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.209 ns" { rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.864 ns ( 45.92 % ) " "Info: Total cell delay = 1.864 ns ( 45.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.195 ns ( 54.08 % ) " "Info: Total interconnect delay = 2.195 ns ( 54.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.059 ns" { clk PL_FSK2:inst5|q1[0] rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "4.059 ns" { clk clk~out0 PL_FSK2:inst5|q1[0] rtl~0 PL_FSK2:inst5|y } { 0.000ns 0.000ns 1.661ns 0.400ns 0.134ns } { 0.000ns 0.725ns 0.698ns 0.366ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.099 ns + Longest register pin " "Info: + Longest register to pin delay is 4.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PL_FSK2:inst5\|y 1 REG LC_X2_Y17_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5\|y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.723 ns) + CELL(2.376 ns) 4.099 ns y 2 PIN PIN_N21 0 " "Info: 2: + IC(1.723 ns) + CELL(2.376 ns) = 4.099 ns; Loc. = PIN_N21; Fanout = 0; PIN Node = 'y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.099 ns" { PL_FSK2:inst5|y y } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 216 608 784 232 "y" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 57.97 % ) " "Info: Total cell delay = 2.376 ns ( 57.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.723 ns ( 42.03 % ) " "Info: Total interconnect delay = 1.723 ns ( 42.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.099 ns" { PL_FSK2:inst5|y y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "4.099 ns" { PL_FSK2:inst5|y y } { 0.000ns 1.723ns } { 0.000ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.059 ns" { clk PL_FSK2:inst5|q1[0] rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "4.059 ns" { clk clk~out0 PL_FSK2:inst5|q1[0] rtl~0 PL_FSK2:inst5|y } { 0.000ns 0.000ns 1.661ns 0.400ns 0.134ns } { 0.000ns 0.725ns 0.698ns 0.366ns 0.075ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.099 ns" { PL_FSK2:inst5|y y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "4.099 ns" { PL_FSK2:inst5|y y } { 0.000ns 1.723ns } { 0.000ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "PL_FSK1:inst\|y x clk -1.567 ns register " "Info: th for register \"PL_FSK1:inst\|y\" (data pin = \"x\", clock pin = \"clk\") is -1.567 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.928 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.542 ns) 2.928 ns PL_FSK1:inst\|y 2 REG LC_X1_Y17_N5 2 " "Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X1_Y17_N5; Fanout = 2; REG Node = 'PL_FSK1:inst\|y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.203 ns" { clk PL_FSK1:inst|y } "NODE_NAME" } "" } } { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.27 % ) " "Info: Total cell delay = 1.267 ns ( 43.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.661 ns ( 56.73 % ) " "Info: Total interconnect delay = 1.661 ns ( 56.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK1:inst|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK1:inst|y } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.595 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.595 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns x 1 PIN PIN_L21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L21; Fanout = 1; PIN Node = 'x'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { x } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 104 104 272 120 "x" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.647 ns) + CELL(0.223 ns) 4.595 ns PL_FSK1:inst\|y 2 REG LC_X1_Y17_N5 2 " "Info: 2: + IC(3.647 ns) + CELL(0.223 ns) = 4.595 ns; Loc. = LC_X1_Y17_N5; Fanout = 2; REG Node = 'PL_FSK1:inst\|y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "3.870 ns" { x PL_FSK1:inst|y } "NODE_NAME" } "" } } { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 20.63 % ) " "Info: Total cell delay = 0.948 ns ( 20.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.647 ns ( 79.37 % ) " "Info: Total interconnect delay = 3.647 ns ( 79.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.595 ns" { x PL_FSK1:inst|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "4.595 ns" { x x~out0 PL_FSK1:inst|y } { 0.000ns 0.000ns 3.647ns } { 0.000ns 0.725ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.928 ns" { clk PL_FSK1:inst|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "2.928 ns" { clk clk~out0 PL_FSK1:inst|y } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "4.595 ns" { x PL_FSK1:inst|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "4.595 ns" { x x~out0 PL_FSK1:inst|y } { 0.000ns 0.000ns 3.647ns } { 0.000ns 0.725ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}