pl_fsk.tan.qmsg

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst5\|q1\[1\] " "Info: Detected ripple clock \"PL_FSK2:inst5\|q1\[1\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst5\|q1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst5\|q1\[2\] " "Info: Detected ripple clock \"PL_FSK2:inst5\|q1\[2\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst5\|q1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst5\|q1\[3\] " "Info: Detected ripple clock \"PL_FSK2:inst5\|q1\[3\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst5\|q1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst5\|xx " "Info: Detected ripple clock \"PL_FSK2:inst5\|xx\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 16 -1 0 } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst5\|xx" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~0 " "Info: Detected gated clock \"rtl~0\" as buffer" {  } { { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "rtl~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst5\|q1\[0\] " "Info: Detected ripple clock \"PL_FSK2:inst5\|q1\[0\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst5\|q1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register PL_FSK2:inst5\|m\[2\] register PL_FSK2:inst5\|y 122.19 MHz 8.184 ns Internal " "Info: Clock \"clk\" has Internal fmax of 122.19 MHz between source register \"PL_FSK2:inst5\|m\[2\]\" and destination register \"PL_FSK2:inst5\|y\" (period= 8.184 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.672 ns + Longest register register " "Info: + Longest register to register delay is 0.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PL_FSK2:inst5\|m\[2\] 1 REG LC_X2_Y17_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N0; Fanout = 2; REG Node = 'PL_FSK2:inst5\|m\[2\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { PL_FSK2:inst5|m[2] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.280 ns) 0.672 ns PL_FSK2:inst5\|y 2 REG LC_X2_Y17_N3 1 " "Info: 2: + IC(0.392 ns) + CELL(0.280 ns) = 0.672 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5\|y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.672 ns" { PL_FSK2:inst5|m[2] PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 41.67 % ) " "Info: Total cell delay = 0.280 ns ( 41.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.392 ns ( 58.33 % ) " "Info: Total interconnect delay = 0.392 ns ( 58.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.672 ns" { PL_FSK2:inst5|m[2] PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "0.672 ns" { PL_FSK2:inst5|m[2] PL_FSK2:inst5|y } { 0.000ns 0.392ns } { 0.000ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.674 ns - Smallest " "Info: - Smallest clock skew is -2.674 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.800 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.698 ns) 3.084 ns PL_FSK2:inst5\|q1\[1\] 2 REG LC_X2_Y17_N8 6 " "Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X2_Y17_N8; Fanout = 6; REG Node = 'PL_FSK2:inst5\|q1\[1\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.359 ns" { clk PL_FSK2:inst5|q1[1] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.075 ns) 3.591 ns rtl~0 3 COMB LC_X2_Y17_N2 4 " "Info: 3: + IC(0.432 ns) + CELL(0.075 ns) = 3.591 ns; Loc. = LC_X2_Y17_N2; Fanout = 4; COMB Node = 'rtl~0'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.507 ns" { PL_FSK2:inst5|q1[1] rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 3.800 ns PL_FSK2:inst5\|y 4 REG LC_X2_Y17_N3 1 " "Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 3.800 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5\|y'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.209 ns" { rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.573 ns ( 41.39 % ) " "Info: Total cell delay = 1.573 ns ( 41.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.227 ns ( 58.61 % ) " "Info: Total interconnect delay = 2.227 ns ( 58.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "3.800 ns" { clk PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "3.800 ns" { clk clk~out0 PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|y } { 0.000ns 0.000ns 1.661ns 0.432ns 0.134ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.474 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.698 ns) 3.084 ns PL_FSK2:inst5\|xx 2 REG LC_X1_Y17_N8 3 " "Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X1_Y17_N8; Fanout = 3; REG Node = 'PL_FSK2:inst5\|xx'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "2.359 ns" { clk PL_FSK2:inst5|xx } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.848 ns) + CELL(0.542 ns) 6.474 ns PL_FSK2:inst5\|m\[2\] 3 REG LC_X2_Y17_N0 2 " "Info: 3: + IC(2.848 ns) + CELL(0.542 ns) = 6.474 ns; Loc. = LC_X2_Y17_N0; Fanout = 2; REG Node = 'PL_FSK2:inst5\|m\[2\]'" {  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "3.390 ns" { PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } "NODE_NAME" } "" } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.965 ns ( 30.35 % ) " "Info: Total cell delay = 1.965 ns ( 30.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.509 ns ( 69.65 % ) " "Info: Total interconnect delay = 4.509 ns ( 69.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "6.474 ns" { clk PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "6.474 ns" { clk clk~out0 PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } { 0.000ns 0.000ns 1.661ns 2.848ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "3.800 ns" { clk PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "3.800 ns" { clk clk~out0 PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|y } { 0.000ns 0.000ns 1.661ns 0.432ns 0.134ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.075ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "6.474 ns" { clk PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "6.474 ns" { clk clk~out0 PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } { 0.000ns 0.000ns 1.661ns 2.848ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.590 ns + " "Info: + Micro setup delay of destination is 0.590 ns" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 37 -1 0 } } { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 10 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "0.672 ns" { PL_FSK2:inst5|m[2] PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "0.672 ns" { PL_FSK2:inst5|m[2] PL_FSK2:inst5|y } { 0.000ns 0.392ns } { 0.000ns 0.280ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "3.800 ns" { clk PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|y } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "3.800 ns" { clk clk~out0 PL_FSK2:inst5|q1[1] rtl~0 PL_FSK2:inst5|y } { 0.000ns 0.000ns 1.661ns 0.432ns 0.134ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.075ns } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "6.474 ns" { clk PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } "NODE_NAME" } "" } } { "d:/quartus ii/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/bin/Technology_Viewer.qrui" "6.474 ns" { clk clk~out0 PL_FSK2:inst5|xx PL_FSK2:inst5|m[2] } { 0.000ns 0.000ns 1.661ns 2.848ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}