pl_fsk.fit.qmsg

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 18 11:18:37 2006 " "Info: Processing started: Sat Mar 18 11:18:37 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PL_FSK -c PL_FSK " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off PL_FSK -c PL_FSK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "PL_FSK EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design PL_FSK" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "5 5 " "Info: No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "c " "Info: Pin c not assigned to an exact location on the device" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 72 480 656 88 "c" "" } } } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "c" } } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { c } "NODE_NAME" } "" } } { "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" "" { c } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "y " "Info: Pin y not assigned to an exact location on the device" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 216 608 784 232 "y" "" } } } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "y" } } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { y } "NODE_NAME" } "" } } { "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" "" { y } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x " "Info: Pin x not assigned to an exact location on the device" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 104 104 272 120 "x" "" } } } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "x" } } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { x } "NODE_NAME" } "" } } { "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" "" { x } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { clk } "NODE_NAME" } "" } } { "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "start " "Info: Pin start not assigned to an exact location on the device" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 56 104 272 72 "start" "" } } } } { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "start" } } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { start } "NODE_NAME" } "" } } { "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" "" { start } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN L2 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN L2" {  } { { "PL_FSK.bdf" "" { Schematic "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf" { { 152 104 272 168 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "PL_FSK2:inst5\|xx Global clock " "Info: Automatically promoted signal \"PL_FSK2:inst5\|xx\" to use Global clock" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 16 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rtl~2 Global clock " "Info: Automatically promoted some destinations of signal \"rtl~2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PL_FSK1:inst\|f1 " "Info: Destination \"PL_FSK1:inst\|f1\" may be non-global or may not use global clock" {  } { { "PL_FSK1.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PL_FSK2:inst5\|q1\[3\] " "Info: Destination \"PL_FSK2:inst5\|q1\[3\]\" may be non-global or may not use global clock" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PL_FSK2:inst5\|q1\[2\] " "Info: Destination \"PL_FSK2:inst5\|q1\[2\]\" may be non-global or may not use global clock" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PL_FSK2:inst5\|q1\[1\] " "Info: Destination \"PL_FSK2:inst5\|q1\[1\]\" may be non-global or may not use global clock" {  } { { "PL_FSK2.vhd" "" { Text "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/quartus ii/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "rtl~2" } } } } { "d:/quartus ii/bin/Report_Window_01.qrpt" "" { Report "d:/quartus ii/bin/Report_Window_01.qrpt" "Compiler" "PL_FSK" "UNKNOWN" "V1" "F:/电子设计/EDA/通信系统调制解调/PL_FSK/db/PL_FSK.quartus_db" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/" "" "" { rtl~2 } "NODE_NAME" } "" } } { "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" { Floorplan "F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.fld" "" "" { rtl~2 } "NODE_NAME" } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0 0 "Start inferring scan chains for DSP blocks" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0 0 "Inferring scan chains for DSP blocks is complete" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}