pl_fsk.hif

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

Version 5.1 Build 176 10/26/2005 SJ Web Edition
37
2006
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
PL_FSK2
# storage
db|PL_FSK.(2).cnf
db|PL_FSK.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
PL_FSK2.vhd
d1a0a474c55ff6391502b1a6f98c3b
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
PL_FSK2:inst5
}
# end
# entity
PL_FSK1
# storage
db|PL_FSK.(1).cnf
db|PL_FSK.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
PL_FSK1.vhd
15b9b2e9afea5678a24b6acf559480bd
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
PL_FSK1:inst
}
# end
# entity
PL_FSK
# storage
db|PL_FSK.(0).cnf
db|PL_FSK.(0).cnf
# case_insensitive
# source_file
PL_FSK.bdf
69dbc5a15da9274149b31ca563f0f528
23
# hierarchies {
|
}
# end
# complete