pl_fsk.tan.summary

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.405 ns
From           : start
To             : PL_FSK2:inst5|q1[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.158 ns
From           : PL_FSK2:inst5|y
To             : y
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.567 ns
From           : x
To             : PL_FSK1:inst|y
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 122.19 MHz ( period = 8.184 ns )
From           : PL_FSK2:inst5|m[2]
To             : PL_FSK2:inst5|y
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : PL_FSK2:inst5|q1[1]
To             : PL_FSK2:inst5|m[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 12

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 12

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