pl_fsk2.vhd

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity PL_FSK2 is
	port(clk:in	std_logic;
	start:in	std_logic;
	x:in	std_logic;
	y:out   std_logic
	);
end PL_FSK2 ;

architecture behv of PL_FSK2  is
	signal q1 : integer range 0 to 11 ;
	signal xx : std_logic ;
	signal m : integer range 0 to 5 ;
begin

process(clk)
	begin
		if clk'event and clk='1' then
		xx<=x;
			if start = '0' then
				q1<=0;
				elsif q1=11 then
				q1<=0;
				else
				q1<=q1+1;
			end if;
		end if;
end process;


process(xx,q1)
	begin
	if q1=11 then
		m<=0;
		elsif q1=10 then
				if m<=3 then y<='0';
						else y<='1';
				end if;
		elsif xx'event and xx='1' then m<=m+1;
	end if;
end process;
	
end behv;