pl_fsk.map.summary

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

Analysis & Synthesis Status : Successful - Sat Mar 18 11:18:32 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : PL_FSK
Top-level Entity Name : PL_FSK
Family : Stratix
Total logic elements : 17
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0