pl_fsk.tan.rpt

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

+-------+--------------+------------+-------+---------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To                  ; To Clock ;
+-------+--------------+------------+-------+---------------------+----------+
; N/A   ; None         ; 2.405 ns   ; start ; PL_FSK2:inst5|q1[0] ; clk      ;
; N/A   ; None         ; 2.359 ns   ; start ; PL_FSK1:inst|f1     ; clk      ;
; N/A   ; None         ; 2.359 ns   ; start ; PL_FSK1:inst|f2     ; clk      ;
; N/A   ; None         ; 2.182 ns   ; start ; PL_FSK2:inst5|q1[3] ; clk      ;
; N/A   ; None         ; 2.180 ns   ; start ; PL_FSK2:inst5|q1[1] ; clk      ;
; N/A   ; None         ; 2.171 ns   ; start ; PL_FSK2:inst5|q1[2] ; clk      ;
; N/A   ; None         ; 1.677 ns   ; x     ; PL_FSK1:inst|y      ; clk      ;
+-------+--------------+------------+-------+---------------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-----------------+----+------------+
; Slack ; Required tco ; Actual tco ; From            ; To ; From Clock ;
+-------+--------------+------------+-----------------+----+------------+
; N/A   ; None         ; 8.158 ns   ; PL_FSK2:inst5|y ; y  ; clk        ;
; N/A   ; None         ; 6.684 ns   ; PL_FSK1:inst|y  ; c  ; clk        ;
+-------+--------------+------------+-----------------+----+------------+


+----------------------------------------------------------------------------------+
; th                                                                               ;
+---------------+-------------+-----------+-------+---------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                  ; To Clock ;
+---------------+-------------+-----------+-------+---------------------+----------+
; N/A           ; None        ; -1.567 ns ; x     ; PL_FSK1:inst|y      ; clk      ;
; N/A           ; None        ; -2.061 ns ; start ; PL_FSK2:inst5|q1[2] ; clk      ;
; N/A           ; None        ; -2.070 ns ; start ; PL_FSK2:inst5|q1[1] ; clk      ;
; N/A           ; None        ; -2.072 ns ; start ; PL_FSK2:inst5|q1[3] ; clk      ;
; N/A           ; None        ; -2.249 ns ; start ; PL_FSK1:inst|f1     ; clk      ;
; N/A           ; None        ; -2.249 ns ; start ; PL_FSK1:inst|f2     ; clk      ;
; N/A           ; None        ; -2.295 ns ; start ; PL_FSK2:inst5|q1[0] ; clk      ;
+---------------+-------------+-----------+-------+---------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Sat Mar 18 11:19:32 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PL_FSK -c PL_FSK --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "PL_FSK2:inst5|y" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "PL_FSK2:inst5|q1[1]" as buffer
    Info: Detected ripple clock "PL_FSK2:inst5|q1[2]" as buffer
    Info: Detected ripple clock "PL_FSK2:inst5|q1[3]" as buffer
    Info: Detected ripple clock "PL_FSK2:inst5|xx" as buffer
    Info: Detected gated clock "rtl~0" as buffer
    Info: Detected ripple clock "PL_FSK2:inst5|q1[0]" as buffer
Info: Clock "clk" has Internal fmax of 122.19 MHz between source register "PL_FSK2:inst5|m[2]" and destination register "PL_FSK2:inst5|y" (period= 8.184 ns)
    Info: + Longest register to register delay is 0.672 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N0; Fanout = 2; REG Node = 'PL_FSK2:inst5|m[2]'
        Info: 2: + IC(0.392 ns) + CELL(0.280 ns) = 0.672 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5|y'
        Info: Total cell delay = 0.280 ns ( 41.67 % )
        Info: Total interconnect delay = 0.392 ns ( 58.33 % )
    Info: - Smallest clock skew is -2.674 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.800 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X2_Y17_N8; Fanout = 6; REG Node = 'PL_FSK2:inst5|q1[1]'
            Info: 3: + IC(0.432 ns) + CELL(0.075 ns) = 3.591 ns; Loc. = LC_X2_Y17_N2; Fanout = 4; COMB Node = 'rtl~0'
            Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 3.800 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5|y'
            Info: Total cell delay = 1.573 ns ( 41.39 % )
            Info: Total interconnect delay = 2.227 ns ( 58.61 % )
        Info: - Longest clock path from clock "clk" to source register is 6.474 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X1_Y17_N8; Fanout = 3; REG Node = 'PL_FSK2:inst5|xx'
            Info: 3: + IC(2.848 ns) + CELL(0.542 ns) = 6.474 ns; Loc. = LC_X2_Y17_N0; Fanout = 2; REG Node = 'PL_FSK2:inst5|m[2]'
            Info: Total cell delay = 1.965 ns ( 30.35 % )
            Info: Total interconnect delay = 4.509 ns ( 69.65 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.590 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "PL_FSK2:inst5|q1[1]" and destination pin or register "PL_FSK2:inst5|m[0]" for clock "clk" (Hold time is 2.4 ns)
    Info: + Largest clock skew is 3.546 ns
        Info: + Longest clock path from clock "clk" to destination register is 6.474 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X1_Y17_N8; Fanout = 3; REG Node = 'PL_FSK2:inst5|xx'
            Info: 3: + IC(2.848 ns) + CELL(0.542 ns) = 6.474 ns; Loc. = LC_X2_Y17_N5; Fanout = 3; REG Node = 'PL_FSK2:inst5|m[0]'
            Info: Total cell delay = 1.965 ns ( 30.35 % )
            Info: Total interconnect delay = 4.509 ns ( 69.65 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.928 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X2_Y17_N8; Fanout = 6; REG Node = 'PL_FSK2:inst5|q1[1]'
            Info: Total cell delay = 1.267 ns ( 43.27 % )
            Info: Total interconnect delay = 1.661 ns ( 56.73 % )
    Info: - Micro clock to output delay of source is 0.156 ns
    Info: - Shortest register to register delay is 1.090 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N8; Fanout = 6; REG Node = 'PL_FSK2:inst5|q1[1]'
        Info: 2: + IC(0.432 ns) + CELL(0.075 ns) = 0.507 ns; Loc. = LC_X2_Y17_N2; Fanout = 4; COMB Node = 'rtl~0'
        Info: 3: + IC(0.360 ns) + CELL(0.223 ns) = 1.090 ns; Loc. = LC_X2_Y17_N5; Fanout = 3; REG Node = 'PL_FSK2:inst5|m[0]'
        Info: Total cell delay = 0.298 ns ( 27.34 % )
        Info: Total interconnect delay = 0.792 ns ( 72.66 % )
    Info: + Micro hold delay of destination is 0.100 ns
Info: tsu for register "PL_FSK2:inst5|q1[0]" (data pin = "start", clock pin = "clk") is 2.405 ns
    Info: + Longest pin to register delay is 5.323 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 6; PIN Node = 'start'
        Info: 2: + IC(4.037 ns) + CELL(0.458 ns) = 5.323 ns; Loc. = LC_X2_Y17_N7; Fanout = 8; REG Node = 'PL_FSK2:inst5|q1[0]'
        Info: Total cell delay = 1.286 ns ( 24.16 % )
        Info: Total interconnect delay = 4.037 ns ( 75.84 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X2_Y17_N7; Fanout = 8; REG Node = 'PL_FSK2:inst5|q1[0]'
        Info: Total cell delay = 1.267 ns ( 43.27 % )
        Info: Total interconnect delay = 1.661 ns ( 56.73 % )
Info: tco from clock "clk" to destination pin "y" through register "PL_FSK2:inst5|y" is 8.158 ns
    Info: + Longest clock path from clock "clk" to source register is 4.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.661 ns) + CELL(0.698 ns) = 3.084 ns; Loc. = LC_X2_Y17_N7; Fanout = 8; REG Node = 'PL_FSK2:inst5|q1[0]'
        Info: 3: + IC(0.400 ns) + CELL(0.366 ns) = 3.850 ns; Loc. = LC_X2_Y17_N2; Fanout = 4; COMB Node = 'rtl~0'
        Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 4.059 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5|y'
        Info: Total cell delay = 1.864 ns ( 45.92 % )
        Info: Total interconnect delay = 2.195 ns ( 54.08 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.099 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N3; Fanout = 1; REG Node = 'PL_FSK2:inst5|y'
        Info: 2: + IC(1.723 ns) + CELL(2.376 ns) = 4.099 ns; Loc. = PIN_N21; Fanout = 0; PIN Node = 'y'
        Info: Total cell delay = 2.376 ns ( 57.97 % )
        Info: Total interconnect delay = 1.723 ns ( 42.03 % )
Info: th for register "PL_FSK1:inst|y" (data pin = "x", clock pin = "clk") is -1.567 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X1_Y17_N5; Fanout = 2; REG Node = 'PL_FSK1:inst|y'
        Info: Total cell delay = 1.267 ns ( 43.27 % )
        Info: Total interconnect delay = 1.661 ns ( 56.73 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.595 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L21; Fanout = 1; PIN Node = 'x'
        Info: 2: + IC(3.647 ns) + CELL(0.223 ns) = 4.595 ns; Loc. = LC_X1_Y17_N5; Fanout = 2; REG Node = 'PL_FSK1:inst|y'
        Info: Total cell delay = 0.948 ns ( 20.63 % )
        Info: Total interconnect delay = 3.647 ns ( 79.37 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Processing ended: Sat Mar 18 11:19:33 2006
    Info: Elapsed time: 00:00:02