📄 pl_fsk.tan.rpt
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Timing Analyzer report for PL_FSK
Sat Mar 18 11:19:34 2006
Version 5.1 Build 176 10/26/2005 SJ Web Edition
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. Clock Hold: 'clk'
7. tsu
8. tco
9. th
10. Timing Analyzer Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+---------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+---------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 2.405 ns ; start ; PL_FSK2:inst5|q1[0] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 8.158 ns ; PL_FSK2:inst5|y ; y ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -1.567 ns ; x ; PL_FSK1:inst|y ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 122.19 MHz ( period = 8.184 ns ) ; PL_FSK2:inst5|m[2] ; PL_FSK2:inst5|y ; clk ; clk ; 0 ;
; Clock Hold: 'clk' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|m[0] ; clk ; clk ; 12 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 12 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+---------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 122.19 MHz ( period = 8.184 ns ) ; PL_FSK2:inst5|m[2] ; PL_FSK2:inst5|y ; clk ; clk ; None ; None ; 0.672 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[2] ; PL_FSK1:inst|f1 ; clk ; clk ; None ; None ; 2.146 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[3] ; PL_FSK1:inst|f1 ; clk ; clk ; None ; None ; 2.132 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|q1[3] ; clk ; clk ; None ; None ; 2.127 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[2] ; PL_FSK2:inst5|q1[3] ; clk ; clk ; None ; None ; 2.059 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[3] ; PL_FSK2:inst5|q1[3] ; clk ; clk ; None ; None ; 2.045 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|q1[3] ; clk ; clk ; None ; None ; 2.034 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|q1[2] ; clk ; clk ; None ; None ; 2.025 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[0] ; PL_FSK1:inst|f1 ; clk ; clk ; None ; None ; 1.996 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[2] ; PL_FSK2:inst5|q1[2] ; clk ; clk ; None ; None ; 1.834 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[2] ; PL_FSK2:inst5|q1[1] ; clk ; clk ; None ; None ; 1.832 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[3] ; PL_FSK2:inst5|q1[2] ; clk ; clk ; None ; None ; 1.820 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[3] ; PL_FSK2:inst5|q1[1] ; clk ; clk ; None ; None ; 1.818 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|q1[2] ; clk ; clk ; None ; None ; 1.814 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|q1[1] ; clk ; clk ; None ; None ; 1.682 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[1] ; PL_FSK1:inst|f1 ; clk ; clk ; None ; None ; 1.679 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|q1[1] ; clk ; clk ; None ; None ; 1.365 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[0] ; PL_FSK1:inst|f2 ; clk ; clk ; None ; None ; 1.120 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|q1[0] ; clk ; clk ; None ; None ; 0.877 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|m[2] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 0.846 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK1:inst|f2 ; PL_FSK1:inst|y ; clk ; clk ; None ; None ; 0.832 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|m[0] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 0.745 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|m[0] ; PL_FSK2:inst5|m[1] ; clk ; clk ; None ; None ; 0.743 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|m[0] ; PL_FSK2:inst5|m[0] ; clk ; clk ; None ; None ; 0.736 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK1:inst|f1 ; PL_FSK1:inst|f1 ; clk ; clk ; None ; None ; 0.726 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK1:inst|f1 ; PL_FSK1:inst|y ; clk ; clk ; None ; None ; 0.726 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|m[1] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 0.650 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK2:inst5|m[1] ; PL_FSK2:inst5|m[1] ; clk ; clk ; None ; None ; 0.646 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; PL_FSK1:inst|y ; PL_FSK2:inst5|xx ; clk ; clk ; None ; None ; 0.485 ns ;
+-------+------------------------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+------------------------------------------+---------------------+--------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------------+--------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|m[0] ; clk ; clk ; None ; None ; 1.090 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[2] ; PL_FSK2:inst5|m[0] ; clk ; clk ; None ; None ; 1.179 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[3] ; PL_FSK2:inst5|m[0] ; clk ; clk ; None ; None ; 1.252 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|m[0] ; clk ; clk ; None ; None ; 1.349 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 1.413 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[1] ; PL_FSK2:inst5|m[1] ; clk ; clk ; None ; None ; 1.415 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[2] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 1.502 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[2] ; PL_FSK2:inst5|m[1] ; clk ; clk ; None ; None ; 1.504 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[3] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 1.575 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[3] ; PL_FSK2:inst5|m[1] ; clk ; clk ; None ; None ; 1.577 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|m[2] ; clk ; clk ; None ; None ; 1.672 ns ;
; Not operational: Clock Skew > Data Delay ; PL_FSK2:inst5|q1[0] ; PL_FSK2:inst5|m[1] ; clk ; clk ; None ; None ; 1.674 ns ;
+------------------------------------------+---------------------+--------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+----------------------------------------------------------------------------+
; tsu ;
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