pl_fsk1.vhd

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity PL_FSK1 is
	port(clk:in	std_logic;
	start:in	std_logic;
	x:in	std_logic;
	y:out   std_logic
	);
end PL_FSK1 ;

architecture behv of PL_FSK1  is
	signal q1 : integer range 0 to 11 ;
	signal q2 : integer range 0 to 1 ;
	signal f1 : std_logic ;
	signal f2 : std_logic ;
begin

process(clk)
	begin
		if clk'event and clk='1' then
			if start = '0' then
				q1<=0;
				elsif q1=5 then
				f1<='1';q1<=q1+1;
				elsif q1=11 then
				f1<='0';q1<=0;
				else
				q1<=q1+1;
			end if;
		end if;
end process;

process(clk)
	begin
		if clk'event and clk='1' then
			if start = '0' then
				q2<=0;
				elsif q2=0 then
				f2<='1';q2<=q2+1;
				elsif q2=1 then
				f2<='0';q2<=0;
				else
				q2<=q2+1;
			end if;
		end if;
end process;

process(clk,x)
	begin
		if clk'event and clk='1' then
			if x = '0' then
			y<=f1;
			else
			y<=f2;
			end if;
		end if;
end process;
	
end behv;