pl_fsk.sim.talkback.xml

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

<!--
This XML file (created on Sat Mar 18 11:30:08 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<nic_id>000c76594cd8</nic_id>
	<cdrive_id>94f662ba</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_sim.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Sat Mar 18 11:30:09 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2020</cpu_freq>
	</cpu>
	<ram units="MB">224</ram>
</machine>
<top_file>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK</top_file>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off PL_FSK -c PL_FSK</command_line>
</mep_data>
<messages>
	<info>Info: Quartus II Simulator was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Sat Mar 18 11:30:08 2006</info>
	<info>Info: Number of transitions in simulation is 973</info>
	<info>Info: Simulation coverage is      94.12 %</info>
</messages>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Timing</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Automatically save/load simulation netlist</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>On</setting>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>1.0 us</simulation_end_time>
	<simulation_netlist_size>22 nodes</simulation_netlist_size>
	<simulation_coverage>     94.12 %</simulation_coverage>
	<total_number_of_transitions>973</total_number_of_transitions>
	<family>Stratix</family>
	<device>EP1S10F484C5</device>
</simulator_summary>
<compile_id>4E111E57</compile_id>
</talkback>