pl_fsk.tan.talkback.xml

用matlab7.0软件对通信信号进行调制数字通信系统通信系统调制解调(PL_FSK)VHDL建模,包括发送和接受模块PL_FSK

<!--
This XML file (created on Sat Mar 18 11:19:34 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<nic_id>000c76594cd8</nic_id>
	<cdrive_id>94f662ba</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Sat Mar 18 11:19:34 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2020</cpu_freq>
	</cpu>
	<ram units="MB">224</ram>
</machine>
<top_file>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off PL_FSK -c PL_FSK --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock &quot;clk&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis is analyzing one or more combinational loops as latches</warning>
	<warning>Warning: Node &quot;PL_FSK2:inst5|y&quot; is a latch</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 5 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Sat Mar 18 11:19:33 2006</info>
	<info>Info: th for register &quot;PL_FSK1:inst|y&quot; (data pin = &quot;x&quot;, clock pin = &quot;clk&quot;) is -1.567 ns</info>
	<info>Info: - Shortest pin to register delay is 4.595 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>2.405 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>8.158 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-1.567 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>122.19 MHz ( period = 8.184 ns )</actual>
	</clk>
</performance>
<compile_id>213D41D2</compile_id>
</talkback>