📄 pl_fsk.fit.talkback.xml
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<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>x</name>
<pin__>L21</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>19</y_coordinate>
<cell_number>3</cell_number>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
</input_pins>
<output_pins>
<row>
<name>c</name>
<pin__>N20</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>11</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>y</name>
<pin__>N21</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>11</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
</output_pins>
<i_o_bank_usage>
<row>
<i_o_bank>1</i_o_bank>
<usage>3 / 29 ( 10 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>2</i_o_bank>
<usage>1 / 30 ( 3 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>3</i_o_bank>
<usage>0 / 51 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>4</i_o_bank>
<usage>1 / 52 ( 2 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>5</i_o_bank>
<usage>1 / 29 ( 3 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>6</i_o_bank>
<usage>0 / 29 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>7</i_o_bank>
<usage>0 / 52 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>8</i_o_bank>
<usage>0 / 51 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>9</i_o_bank>
<usage>0 / 6 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>11</i_o_bank>
<usage>0 / 6 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
</i_o_bank_usage>
<advanced_data___general>
<row>
<name>Status Code</name>
<value>0</value>
</row>
<row>
<name>Desired User Slack</name>
<value>0</value>
</row>
<row>
<name>Fit Attempts</name>
<value>1</value>
</row>
</advanced_data___general>
<advanced_data___placement_preparation>
<row>
<name>Auto Fit Point 1 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>497145</value>
</row>
<row>
<name>Internal Atom Count - Fit Attempt 1</name>
<value>18</value>
</row>
<row>
<name>LE/ALM Count - Fit Attempt 1</name>
<value>18</value>
</row>
<row>
<name>LAB Count - Fit Attempt 1</name>
<value>3</value>
</row>
<row>
<name>Outputs per Lab - Fit Attempt 1</name>
<value>3.333</value>
</row>
<row>
<name>Inputs per LAB - Fit Attempt 1</name>
<value>3.333</value>
</row>
<row>
<name>Global Inputs per LAB - Fit Attempt 1</name>
<value>1.333</value>
</row>
<row>
<name>LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1</name>
<value>0:3</value>
</row>
<row>
<name>LAB Constraint 'ce + sync load' - Fit Attempt 1</name>
<value>0:2;1:1</value>
</row>
<row>
<name>LAB Constraint 'non-global controls' - Fit Attempt 1</name>
<value>0:2;1:1</value>
</row>
<row>
<name>LAB Constraint 'un-route combination' - Fit Attempt 1</name>
<value>0:2;1:1</value>
</row>
<row>
<name>LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1</name>
<value>0:1;1:2</value>
</row>
<row>
<name>LAB Constraint 'un-route with async_clear' - Fit Attempt 1</name>
<value>0:1;1:2</value>
</row>
<row>
<name>LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1</name>
<value>0:3</value>
</row>
<row>
<name>LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1</name>
<value>0:3</value>
</row>
<row>
<name>LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1</name>
<value>0:2;1:1</value>
</row>
<row>
<name>LAB Constraint 'global control signals' - Fit Attempt 1</name>
<value>0:1;1:1;3:1</value>
</row>
<row>
<name>LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1</name>
<value>0:1;2:2</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1</name>
<value>0:3</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair' - Fit Attempt 1</name>
<value>0:1;1:1;2:1</value>
</row>
<row>
<name>LAB Constraint 'sload_sclear pair' - Fit Attempt 1</name>
<value>0:3</value>
</row>
<row>
<name>LAB Constraint 'invert_a constraint' - Fit Attempt 1</name>
<value>0:1;1:2</value>
</row>
<row>
<name>LAB Constraint 'has placement constraint' - Fit Attempt 1</name>
<value>0:3</value>
</row>
<row>
<name>LEs in Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>LEs in Long Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>LABs with Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>LABs with Multiple Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.016</value>
</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
<row>
<name>Auto Fit Point 2 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>496017</value>
</row>
<row>
<name>Auto Fit Point 3 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>496017</value>
</row>
<row>
<name>Auto Fit Point 4 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>496017</value>
</row>
<row>
<name>Auto Fit Point 5 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_dat.dll - Fit Attempt 1</name>
<value>0.156</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.110</value>
</row>
</advanced_data___placement>
<advanced_data___routing>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>495294</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Peak Regional Wire - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>495135</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>495135</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>495135</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.110</value>
</row>
</advanced_data___routing>
<compilation_summary>
<flow_status>Successful - Sat Mar 18 11:19:12 2006</flow_status>
<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
<revision_name>PL_FSK</revision_name>
<top_level_entity_name>PL_FSK</top_level_entity_name>
<family>Stratix</family>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>17 / 10,570 ( < 1 % )</total_logic_elements>
<total_pins>5 / 336 ( 1 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>0 / 920,448 ( 0 % )</total_memory_bits>
<dsp_block_9_bit_elements>0 / 48 ( 0 % )</dsp_block_9_bit_elements>
<total_plls>0 / 6 ( 0 % )</total_plls>
<total_dlls>0 / 2 ( 0 % )</total_dlls>
<device>EP1S10F484C5</device>
<timing_models>Final</timing_models>
</compilation_summary>
<compile_id>B963C88A</compile_id>
<files>
<top>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf</top>
<extensions>
<ext ext_name="vhd">2</ext>
<ext ext_name="bdf">1</ext>
<ext ext_name="vwf">1</ext>
</extensions>
<sub_files>
<sub_file>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK2.vhd</sub_file>
<sub_file>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK1.vhd</sub_file>
<sub_file>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.bdf</sub_file>
<sub_file>F:/电子设计/EDA/通信系统调制解调/PL_FSK/PL_FSK.vwf</sub_file>
</sub_files>
</files>
<architecture>
<family>Stratix</family>
<auto_device>ON</auto_device>
<device>EP1S10F484C5</device>
</architecture>
<pkg_io>
<pin_std count="6">LVTTL</pin_std>
</pkg_io>
<research>
<le_sclr>0</le_sclr>
<le_aclr>11</le_aclr>
<le_aload>0</le_aload>
<le_sload>1</le_sload>
<le_inverta>0</le_inverta>
<le_carry_in>0</le_carry_in>
<le_ce>2</le_ce>
<le_clk>11</le_clk>
<le_ce_sload>0</le_ce_sload>
<pin_sclr>0</pin_sclr>
<pin_aclr>0</pin_aclr>
<pin_ce_in>0</pin_ce_in>
<pin_ce_out>0</pin_ce_out>
</research>
</talkback>
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