stm8s_tim3.c

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  * None
  */
void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_TIM3_IT_OK(TIM3_IT));
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  if (NewState != DISABLE)
  {
    /* Enable the Interrupt sources */
    TIM3->IER |= (u8)TIM3_IT;
  }
  else
  {
    /* Disable the Interrupt sources */
    TIM3->IER &= (u8)(~TIM3_IT);
  }
}


/**
  * @brief Enables or Disables the TIM3 Update event.
  * @param[in] NewState new state of the TIM3 peripheral Preload register. This parameter can
  * be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_UpdateDisableConfig(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the UDIS Bit */
  if (NewState != DISABLE)
  {
    TIM3->CR1 |= TIM3_CR1_UDIS;
  }
  else
  {
    TIM3->CR1 &= (u8)(~TIM3_CR1_UDIS);
  }
}

/**
  * @brief Selects the TIM3 Update Request Interrupt source.
  * @param[in] TIM3_UpdateSource specifies the Update source.
  * This parameter can be one of the following values
  *                       - TIM3_UPDATESOURCE_REGULAR
  *                       - TIM3_UPDATESOURCE_GLOBAL
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
{
  /* Check the parameters */
  assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));

  /* Set or Reset the URS Bit */
  if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
  {
    TIM3->CR1 |= TIM3_CR1_URS;
  }
  else
  {
    TIM3->CR1 &= (u8)(~TIM3_CR1_URS);
  }
}


/**
  * @brief Selects the TIM3抯 One Pulse Mode.
  * @param[in] TIM3_OPMode specifies the OPM Mode to be used.
  * This parameter can be one of the following values
  *                    - TIM3_OPMODE_SINGLE
  *                    - TIM3_OPMODE_REPETITIVE
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
{
  /* Check the parameters */
  assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));

  /* Set or Reset the OPM Bit */
  if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
  {
    TIM3->CR1 |= TIM3_CR1_OPM;
  }
  else
  {
    TIM3->CR1 &= (u8)(~TIM3_CR1_OPM);
  }

}


/**
  * @brief Configures the TIM3 Prescaler.
  * @param[in] Prescaler specifies the Prescaler Register value
  * This parameter can be one of the following values
  *                       -  TIM3_PRESCALER_1
  *                       -  TIM3_PRESCALER_2
  *                       -  TIM3_PRESCALER_4
  *                       -  TIM3_PRESCALER_8
  *                       -  TIM3_PRESCALER_16
  *                       -  TIM3_PRESCALER_32
  *                       -  TIM3_PRESCALER_64
  *                       -  TIM3_PRESCALER_128
  *                       -  TIM3_PRESCALER_256
  *                       -  TIM3_PRESCALER_512
  *                       -  TIM3_PRESCALER_1024
  *                       -  TIM3_PRESCALER_2048
  *                       -  TIM3_PRESCALER_4096
  *                       -  TIM3_PRESCALER_8192
  *                       -  TIM3_PRESCALER_16384
  *                       -  TIM3_PRESCALER_32768
  * @param[in] TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode.
  * This parameter can be one of the following values
  *                       - TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
  *                         immediatly.
  *                       - TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
  *                         the update event.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
                          TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
{
  /* Check the parameters */
  assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
  assert_param(IS_TIM3_PRESCALER_OK(Prescaler));

  /* Set the Prescaler value */
  TIM3->PSCR = (u8)Prescaler;

  /* Set or reset the UG Bit */
  TIM3->EGR = (u8)TIM3_PSCReloadMode;
}

/**
  * @brief Forces the TIM3 Channel1 output waveform to active or inactive level.
  * @param[in] TIM3_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
  *                       - TIM3_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC1REF.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));

  /* Reset the OCM Bits & Configure the Forced output Mode */
  TIM3->CCMR1 =  (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM))  | (u8)TIM3_ForcedAction);
}

/**
  * @brief Forces the TIM3 Channel2 output waveform to active or inactive level.
  * @param[in] TIM3_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
  *                       - TIM3_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC2REF.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));

  /* Reset the OCM Bits & Configure the Forced output Mode */
  TIM3->CCMR2 =  (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
}


/**
  * @brief Enables or disables TIM3 peripheral Preload register on ARR.
  * @param[in] NewState new state of the TIM3 peripheral Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_ARRPreloadConfig(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the ARPE Bit */
  if (NewState != DISABLE)
  {
    TIM3->CR1 |= TIM3_CR1_ARPE;
  }
  else
  {
    TIM3->CR1 &= (u8)(~TIM3_CR1_ARPE);
  }
}


/**
  * @brief Enables or disables the TIM3 peripheral Preload Register on CCR1.
  * @param[in] NewState new state of the Capture Compare Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_OC1PreloadConfig(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the OC1PE Bit */
  if (NewState != DISABLE)
  {
    TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
  }
  else
  {
    TIM3->CCMR1 &= (u8)(~TIM3_CCMR_OCxPE);
  }
}


/**
  * @brief Enables or disables the TIM3 peripheral Preload Register on CCR2.
  * @param[in] NewState new state of the Capture Compare Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_OC2PreloadConfig(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the OC2PE Bit */
  if (NewState != DISABLE)
  {
    TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
  }
  else
  {
    TIM3->CCMR2 &= (u8)(~TIM3_CCMR_OCxPE);
  }
}

/**
  * @brief Configures the TIM3 event to be generated by software.
  * @param[in] TIM3_EventSource specifies the event source.
  * This parameter can be one of the following values:
  *                       - TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
  *                       - TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
  *                       - TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
{
  /* Check the parameters */
  assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));

  /* Set the event sources */
  TIM3->EGR = (u8)TIM3_EventSource;
}


/**
  * @brief Configures the TIM3 Channel 1 polarity.
  * @param[in] TIM3_OCPolarity specifies the OC1 Polarity.
  * This parameter can be one of the following values:
  *                       - TIM3_OCPOLARITY_LOW: Output Compare active low
  *                       - TIM3_OCPOLARITY_HIGH: Output Compare active high
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
{
  /* Check the parameters */
  assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));

  /* Set or Reset the CC1P Bit */
  if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
  {
    TIM3->CCER1 |= TIM3_CCER1_CC1P;
  }
  else
  {
    TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
  }
}


/**
  * @brief Configures the TIM3 Channel 2 polarity.
  * @param[in] TIM3_OCPolarity specifies the OC2 Polarity.
  * This parameter can be one of the following values:
  *                       - TIM3_OCPOLARITY_LOW: Output Compare active low
  *                       - TIM3_OCPOLARITY_HIGH: Output Compare active high
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
{
  /* Check the parameters */
  assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));

  /* Set or Reset the CC2P Bit */
  if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
  {
    TIM3->CCER1 |= TIM3_CCER1_CC2P;
  }
  else
  {
    TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
  }
}