stm8s_tim1.c

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  assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
  assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
  assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));

  /* Configure the TIM1 Input Clock Source */
  if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
  {
    TI2_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter);
  }
  else
  {
    TI1_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter);
  }

  /* Select the Trigger source */
  TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);

  /* Select the External clock mode1 */
  TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1);
}

/**
  * @brief Selects the TIM1 Input Trigger source.
  * @param[in] TIM1_InputTriggerSource specifies Input Trigger source.
  * This parameter can be one of the following values:
  *                       - TIM1_TS_TI1F_ED: TI1 Edge Detector
  *                       - TIM1_TS_TI1FP1: Filtered Timer Input 1
  *                       - TIM1_TS_TI2FP2: Filtered Timer Input 2
  *                       - TIM1_TS_ETRF: External Trigger input
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
{
  /* Check the parameters */
  assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));

  /* Select the Tgigger Source */
  TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource);
}


/**
  * @brief Enables or Disables the TIM1 Update event.
  * @param[in] NewState new state of the TIM1 peripheral Preload register. This parameter can
  * be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */

void TIM1_UpdateDisableConfig(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the UDIS Bit */
  if (NewState != DISABLE)
  {
    TIM1->CR1 |= TIM1_CR1_UDIS;
  }
  else
  {
    TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS);
  }
}

/**
  * @brief Selects the TIM1 Update Request Interrupt source.
  * @param[in] TIM1_UpdateSource specifies the Update source.
  * This parameter can be one of the following values
  *                       - TIM1_UPDATESOURCE_REGULAR
  *                       - TIM1_UPDATESOURCE_GLOBAL
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
{
  /* Check the parameters */
  assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));

  /* Set or Reset the URS Bit */
  if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
  {
    TIM1->CR1 |= TIM1_CR1_URS;
  }
  else
  {
    TIM1->CR1 &= (u8)(~TIM1_CR1_URS);
  }
}


/**
  * @brief Enables or Disables the TIM1抯 Hall sensor interface.
  * @param[in] NewState new state of the TIM1 Hall sensor interface.This parameter can
  * be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_SelectHallSensor(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the TI1S Bit */
  if (NewState != DISABLE)
  {
    TIM1->CR2 |= TIM1_CR2_TI1S;
  }
  else
  {
    TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S);
  }
}


/**
  * @brief Selects the TIM1抯 One Pulse Mode.
  * @param[in] TIM1_OPMode specifies the OPM Mode to be used.
  * This parameter can be one of the following values
  *                    - TIM1_OPMODE_SINGLE
  *                    - TIM1_OPMODE_REPETITIVE
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
{
  /* Check the parameters */
  assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));

  /* Set or Reset the OPM Bit */
  if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
  {
    TIM1->CR1 |= TIM1_CR1_OPM;
  }
  else
  {
    TIM1->CR1 &= (u8)(~TIM1_CR1_OPM);
  }

}


/**
  * @brief Selects the TIM1 Trigger Output Mode.
  * @param[in] TIM1_TRGOSource specifies the Trigger Output source.
  * This parameter can be one of the following values
  *                       - TIM1_TRGOSOURCE_RESET
  *                       - TIM1_TRGOSOURCE_ENABLE
  *                       - TIM1_TRGOSOURCE_UPDATE
  *                       - TIM1_TRGOSource_OC1
  *                       - TIM1_TRGOSOURCE_OC1REF
  *                       - TIM1_TRGOSOURCE_OC2REF
  *                       - TIM1_TRGOSOURCE_OC3REF
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
{

  /* Check the parameters */
  assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
  /* Reset the MMS Bits & Select the TRGO source */
  TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS    )) | (u8)  TIM1_TRGOSource);
}

/**
  * @brief Selects the TIM1 Slave Mode.
  * @param[in] TIM1_SlaveMode specifies the TIM1 Slave Mode.
  * This parameter can be one of the following values
  *                       - TIM1_SLAVEMODE_RESET
  *                       - TIM1_SLAVEMODE_GATED
  *                       - TIM1_SLAVEMODE_TRIGGER
  *                       - TIM1_SLAVEMODE_EXTERNAL1
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
{

  /* Check the parameters */
  assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));

  /* Reset the SMS Bits */ /* Select the Slave Mode */
  TIM1->SMCR = (u8)((TIM1->SMCR &  (u8)(~TIM1_SMCR_SMS)) |  (u8)TIM1_SlaveMode);

}

/**
  * @brief Sets or Resets the TIM1 Master/Slave Mode.
  * @param[in] NewState new state of the synchronization between TIM1 and its slaves
  *  (through TRGO). This parameter can be ENABLE or DISABLE.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONALSTATE_OK(NewState));

  /* Set or Reset the MSM Bit */
  if (NewState != DISABLE)
  {
    TIM1->SMCR |= TIM1_SMCR_MSM;
  }
  else
  {
    TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM);
  }
}

/**
  * @brief Configures the TIM1 Encoder Interface.
  * @param[in] TIM1_EncoderMode specifies the TIM1 Encoder Mode.
  * This parameter can be one of the following values
  *         - TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge
  *                         depending on TI2FP2 level.
  *                       - TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge
  *                         depending on TI1FP1 level.
  *                       - TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and
  *                         TI2FP2 edges depending on the level of the other input.
  * @param[in] TIM1_IC1Polarity specifies the IC1 Polarity.
  * This parameter can be one of the following values
  *                       - TIM1_ICPOLARITY_FALLING
  *                       - TIM1_ICPOLARITY_RISING
  * @param[in] TIM1_IC2Polarity specifies the IC2 Polarity.
  * This parameter can be one of the following values
  *                       - TIM1_ICPOLARITY_FALLING
  *                       - TIM1_ICPOLARITY_RISING
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
                                 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
                                 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
{


  /* Check the parameters */
  assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
  assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
  assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));

  /* Set the TI1 and the TI2 Polarities */
  if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
  {
    TIM1->CCER1 |= TIM1_CCER1_CC1P;
  }
  else
  {
    TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P);
  }

  if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
  {
    TIM1->CCER1 |= TIM1_CCER1_CC2P;
  }
  else
  {
    TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P);
  }
  /* Set the encoder Mode */
  TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode);

  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS))  | (u8) CCMR_TIxDirect_Set);
  TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);

}

/**
  * @brief Configures the TIM1 Prescaler.
  * @param[in] Prescaler specifies the Prescaler Register value
  * This parameter must be a value between 0x0000 and 0xFFFF
  * @param[in] TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode.
  * This parameter can be one of the following values
  *                       - TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
  *                         immediately.
  *                       - TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
  *                         the update event.
  * @retval None
  * @par Required preconditions:
  * None
  */

void TIM1_PrescalerConfig(u16 Prescaler,
                          TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
{
  /* Check the parameters */
  assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));

  /* Set the Prescaler value */
  TIM1->PSCRH = (u8)(Prescaler >> 8);
  TIM1->PSCRL = (u8)(Prescaler);

  /* Set or reset the UG Bit */
  TIM1->EGR = (u8)TIM1_PSCReloadMode;

}

/**
  * @brief Specifies the TIM1 Counter Mode to be used.
  * @param[in] TIM1_CounterMode specifies the Counter Mode to be used
  * This parameter can be one of the following values:
  *                       - TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
  *                       - TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
  *                       - TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
  *                       - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
  *                       - TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
{
  /* Check the parameters */
  assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));


  /* Reset the CMS and DIR Bits & Set the Counter Mode */
  TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode);
}


/**
  * @brief Forces the TIM1 Channel1 output waveform to active or inactive level.
  * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
  *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC1REF.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));

  /* Reset the OCM Bits & Configure the Forced output Mode */
  TIM1->CCMR1 =  (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM))  | (u8)TIM1_ForcedAction);
}


/**
  * @brief Forces the TIM1 Channel2 output waveform to active or inactive level.
  * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
  *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC2REF.
  * @retval None
  * @par Required preconditions:
  * None
  */
void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));

  /* Reset the OCM Bits & Configure the Forced output Mode */
  TIM1->CCMR2  =  (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
}


/**
  * @brief Forces the TIM1 Channel3 output waveform to active or inactive level.
  * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
  *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC3REF.
  * @retval None
  * @par Required preconditions:
  * None