sram216.v

SRAM IS61LVC12824,读写控制程序

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:48:22 05/12/2009 
// Design Name: 
// Module Name:    sram216 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module sram216(clk,res,ctr,resout,adrctr,noe,nwe,dio,led);
input clk,res,ctr;
output noe,nwe,adrctr,resout;
output [3:0] led;
wire	 [3:0] led;
reg 	noe,nwe,adrctr;
wire resout;
inout [23:0] dio;
reg [23:0] dataout;
wire [23:0] datain;


reg	[1:0] wrstate,rdstate,next_wrstate,next_rdstate;
reg out_en;
reg in_en;

reg [1:0] r0;
reg clk32;

parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;
parameter s3 = 2'b11;

assign resout = res;
assign led = datain[15:12];

assign dio = out_en ? dataout : 24'bz;
assign datain = in_en?dio:datain;

/*
always @(posedge clk or negedge res)
	begin
		if(!res)
		   begin
		      r0<=2'b00;
			   clk32<=1'b0;
			end
		else
			begin
				r0<=r0 + 2'b01;
				if(r0 == 2'b11)
					clk32 <= ~clk32;
				else
					clk32<=clk32;
			end
	end
*/
	
always @(posedge clk or negedge res)
	begin
		if(!res)
			begin
				wrstate<=s0;
				rdstate<=s0;
			end
		else
			begin
				wrstate<=next_wrstate;
				rdstate<=next_rdstate;
			end
	end
		

always @(wrstate or rdstate or res or ctr)						// ctr = 1 wr;  ctr = 0 rd
	begin
		if(!res)
			begin
				out_en<=1'b0;
				in_en<=1'b0;
				noe<=1'b1;
				nwe<=1'b1;
			end
		else
		if(!ctr)																
		   begin
				next_wrstate=s0;
				case(rdstate)							//rd
					s0:
						begin
							out_en<=1'b0;
							adrctr<=1'b1;
							noe<=1'b0;
							nwe<=1'b1;					
							next_rdstate=s1;
						end
					s1:
						begin
							in_en<=1'b1;
							next_rdstate=s2;
						end
					s2:
						begin
							adrctr<=1'b0;
							next_rdstate=s0;
						end
			endcase
			end
		else
			begin
				next_rdstate=s0;
				case(wrstate)									//wr
					s0:
						begin
							in_en<=1'b0;
							adrctr<=1'b1;
							noe<=1'b0;
							nwe<=1'b0;					
							next_wrstate=s1;
						end
					s1:
						begin
							out_en <=1'b1;
							next_wrstate=s2;
						end
					s2:
						begin
							nwe<=1'b1;
							next_wrstate=s3;
						end
					s3:
						begin
							adrctr<=1'b0;
							out_en<=1'b0;
							next_wrstate=s0;
						end
				endcase
			end
	end

always @(posedge clk or negedge res)
   begin
       if(!res)
          dataout<=24'b1000_1001_1010_1011_1100_1101;
        else
           dataout<=dataout;
   end

endmodule