📄 sja1000.h
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/*******************************************************************************
FILE NAME: sja1000.h
PROJECT: Linux DAQ1273 driver, library, and sample programs
FILE DESCRIPTION: This header file contains Philips Semiconductors
SJA1000 CAN controller chip definitions.
Copyright (c) 2006 Eurotech Finland.
For driver version, compiler, and target information, please refer to the
file README.TXT.
ReWrite by Shangyuan Li, Tsinghua Univ.,
Date : 2007-07-27
Version : 1.1
Comment : Add sja1000 base address to the file
Date : 2007-08-17
Version : 1.2
Comment : Move function declarations here
*******************************************************************************/
#ifndef __XKCAN_SJA1000_H_
#define __XKCAN_SJA1000_H_
#include "xkcan_defs.h"
#define SJA1000_BASE 0//0xBF00
extern void wbyte( ubyte, ubyte );
extern ubyte rbyte( ubyte );
extern void SJAReset( );
enum
/* register adrress mapping, PeliCAN mode only */
/* OP - operating mode, SET - reset mode */
/* SFF - Standard Frame Format, EFF - Extended Frame Format */
/* RO - Read Only, WO - Write Only, RW - Read/Write */
{
/* Mode Register */
SJA1000_MOD = 0 + SJA1000_BASE, /* RW */
SJA1000_MOD_RM = 0x01, /* reset mode */
SJA1000_MOD_LOM = 0x02, /* listen only mode */
SJA1000_MOD_STM = 0x04, /* self test mode */
SJA1000_MOD_AFM = 0x08, /* accept filter: 1=single/0=dual */
SJA1000_MOD_AFM_SINGLE = SJA1000_MOD_AFM,
SJA1000_MOD_SM = 0x10, /* sleep mode */
SJA1000_MOD_RSRV = 0xE0, /* reserved, read 0 */
/* Command Register */
SJA1000_CMR = 1 + SJA1000_BASE, /* WO, read: 0 */
SJA1000_CMR_TR = 0x01, /* Transmission Request */
SJA1000_CMR_AT = 0x02, /* Abort Transmission */
SJA1000_CMR_RRB = 0x04, /* Release Rcv Buf */
SJA1000_CMR_CDO = 0x08, /* Clear Data Overrun */
SJA1000_CMR_SRR = 0x10, /* Self Reception Request */
SJA1000_CMR_RSRV = 0xE0, /* Reserved */
/* Status Register */
SJA1000_SR = 2 + SJA1000_BASE, /* RO */
SJA1000_SR_RBS = 0x01, /* Recieve Buffer */
SJA1000_SR_DOS = 0x02, /* Data Overrun */
SJA1000_SR_TBS = 0x04, /* Transmit Buffer Released */
SJA1000_SR_TCS = 0x08, /* Transmission Complete */
SJA1000_SR_RS = 0x10, /* Recieve Status */
SJA1000_SR_TS = 0x20, /* Transmit Status */
SJA1000_SR_ES = 0x40, /* Error Counters warning limit reached */
SJA1000_SR_BS = 0x80, /* Bus Status (1:off) */
/* Interrupt Register */
SJA1000_IR = 3 + SJA1000_BASE, /* RO */
SJA1000_IR_RI = 0x01, /* Receive Interrupt */
SJA1000_IR_RI_SHIFT = 0,
SJA1000_IR_TI = 0x02, /* Transmit Interrupt */
SJA1000_IR_TI_SHIFT = 1,
SJA1000_IR_EI = 0x04, /* Error Warning Intr. */
SJA1000_IR_EI_SHIFT = 2,
SJA1000_IR_DOI = 0x08, /* Data Overrun Intr. */
SJA1000_IR_DOI_SHIFT = 3,
SJA1000_IR_WUI = 0x10, /* Wake Up Interrupt */
SJA1000_IR_WUI_SHIFT = 4,
SJA1000_IR_EPI = 0x20, /* Error Passive Intr. */
SJA1000_IR_EPI_SHIFT = 5,
SJA1000_IR_ALI = 0x40, /* Arbitration Lost Intr. */
SJA1000_IR_ALI_SHIFT = 6,
SJA1000_IR_BEI = 0x80, /* Bus Error Intr. */
SJA1000_IR_BEI_SHIFT = 7,
/* Interrupt Enable Register */
SJA1000_IER = 4 + SJA1000_BASE, /* RW */
SJA1000_IER_RIE = 0x01, /* Receive Intr. Enable */
SJA1000_IER_TIE = 0x02, /* Transmit Intr. Enable */
SJA1000_IER_EIE = 0x04, /* Error Warn. Intr. Enable */
SJA1000_IER_DOIE = 0x08, /* Data Overrun Enable */
SJA1000_IER_WUIE = 0x10, /* Wake Up Intr. Enable */
SJA1000_IER_EPIE = 0x20, /* Error Passive Intr. Enable */
SJA1000_IER_ALIE = 0x40, /* Arbitration Lost Intr. Enable */
SJA1000_IER_BEIE = 0x80, /* Bus Error Intr. Enable */
SJA1000_RSRV_0 = 5 + SJA1000_BASE, /* RO, read: 0 */
/* Bus Timing Register 0 */
SJA1000_BTR0 = 6 + SJA1000_BASE, /* OP:RO, SET:RW */
SJA1000_BTR0_BRP = 0x3F, /* Baud Rate Prescaler */
SJA1000_BTR0_SJW = 0xC0, /* Synchronisation Jump Width */
/* Bus Timing Register 1 */
SJA1000_BTR1 = 7 + SJA1000_BASE, /* OP:RO, SET:RW */
SJA1000_BTR1_TSEG1 = 0x0F,
SJA1000_BTR1_TSEG2 = 0x70,
SJA1000_BTR1_SAM = 0x80, /* Triple sampling */
/* Output Control Register */
SJA1000_OCR = 8 + SJA1000_BASE, /* OP:RO, SET:RW */
SJA1000_OCR_MODE = 0x03,
SJA1000_OCR_MODE_BIPHASE = 0x00,
SJA1000_OCR_MODE_TEST = 0x01,
SJA1000_OCR_MODE_NORMAL = 0x02,
SJA1000_OCR_MODE_CLOCK = 0x03,
SJA1000_OCR_POL0 = 0x04, /* polarity */
SJA1000_OCR_TN0 = 0x08,
SJA1000_OCR_TP0 = 0x10,
SJA1000_OCR_POL1 = 0x20, /* polarity */
SJA1000_OCR_TN1 = 0x40,
SJA1000_OCR_TP1 = 0x80,
/* aliases */
SJA1000_OCR_TX0_PULL_UP = SJA1000_OCR_TP0,
SJA1000_OCR_TX1_PULL_UP = SJA1000_OCR_TP1,
SJA1000_OCR_TX0_PULL_DOWN = SJA1000_OCR_TN0,
SJA1000_OCR_TX1_PULL_DOWN = SJA1000_OCR_TN1,
SJA1000_OCR_TX0_PUSHPULL = SJA1000_OCR_TN0|SJA1000_OCR_TP0,
SJA1000_OCR_TX1_PUSHPULL = SJA1000_OCR_TN1|SJA1000_OCR_TP1,
SJA1000_OCR_TX0_FLOAT = 0x00, /* Z-state */
SJA1000_OCR_TX1_FLOAT = 0x00, /* Z-state */
SJA1000_TEST_0 = 9 + SJA1000_BASE, /* don't write! */
SJA1000_RSRV_1 = 10 + SJA1000_BASE, /* RO, read: 0 */
/* Arbitration Lost Capture Register */
SJA1000_ALC = 11 + SJA1000_BASE, /* RO */
SJA1000_ALC_MASK = 0x1F,
SJA1000_ALC_MASK_ZERO = 0xE0,
/* Error Code Capture Register */
SJA1000_ECC = 12 + SJA1000_BASE, /* RO */
SJA1000_ECC_SEG = 0x1F, /* Segment */
SJA1000_ECC_DIR = 0x20, /* Direction (1=rx, 0=tx */
SJA1000_ECC_ERRC = 0xC0, /* Error Code */
SJA1000_ECC_ERRC_BIT = 0x00,
SJA1000_ECC_ERRC_FORM = 0x40,
SJA1000_ECC_ERRC_STUFF = 0x80,
SJA1000_ECC_ERRC_OTHER = 0xC0,
/* Error Warning Limit Register */
SJA1000_EWLR = 13 + SJA1000_BASE, /* OP:RO, SET:RW */
/* RX Error Counter Register */
SJA1000_RXERR = 14 + SJA1000_BASE, /* OP:RO, SET:RW */
/* TX Error Counter Register */
SJA1000_TXERR = 15 + SJA1000_BASE, /* OP:RO, SET:RW */
/* RX/TX Frame Information */
SJA1000_RX_FI = 16 + SJA1000_BASE, /* OP:RO */
SJA1000_TX_FI = 16 + SJA1000_BASE, /* OP:WO */
SJA1000_FI_DLC = 0x0F, /* Data Length Code */
SJA1000_FI_DONT_CARE = 0x30, /* always 0 for RX FI */
SJA1000_FI_RTR = 0x40, /* Remote Transmission Req */
SJA1000_FI_FF = 0x80, /* Frame Format */
// SJA1000_FI_FF_EXTENDED = 0x80, /* EFF */
//#if 0
SJA1000_FI_FF_STANDARD = 0x00, /* SFF */
//#endif
/* RX/TX ID (Standard Frame Format) */
SJA1000_SFF_RX_ID_BEGIN = 17 + SJA1000_BASE, /* OP:RO */
SJA1000_SFF_TX_ID_BEGIN = 17 + SJA1000_BASE, /* OP:WO */
SJA1000_SFF_RX_ID_END = 18 + SJA1000_BASE, /* OP:RO */
SJA1000_SFF_RX_ID_END_ZERO_MASK = 0x0F, /* always 0 */
SJA1000_SFF_TX_ID_END = 18 + SJA1000_BASE, /* OP:WO */
/* RX/TX DATA (Standard Frame Format) */
SJA1000_SFF_RX_DATA_BEGIN = 19 + SJA1000_BASE, /* OP:RO */
SJA1000_SFF_TX_DATA_BEGIN = 19 + SJA1000_BASE, /* OP:WO */
/* ................... ..... */
SJA1000_SFF_RX_DATA_END = 26 + SJA1000_BASE, /* OP:RO */
SJA1000_SFF_TX_DATA_END = 26 + SJA1000_BASE, /* OP:WO */
/* RX/TX ID (Extended Frame Format) */
SJA1000_EFF_RX_ID_BEGIN = 17 + SJA1000_BASE, /* OP:RO */
SJA1000_EFF_TX_ID_BEGIN = 17 + SJA1000_BASE, /* OP:WO */
/* ................... ..... */
SJA1000_EFF_RX_ID_END = 20 + SJA1000_BASE, /* OP:RO */
JA1000_EFF_RX_ID_END_ZERO_MASK = 0x03, /* always 0 */
SJA1000_EFF_TX_ID_END = 20 + SJA1000_BASE, /* OP:WO */
/* RX/TX DATA (Extended Frame Format) */
SJA1000_EFF_RX_DATA_BEGIN = 21 + SJA1000_BASE, /* OP:RO */
SJA1000_EFF_TX_DATA_BEGIN = 21 + SJA1000_BASE, /* OP:WO */
/* ................... ..... */
SJA1000_EFF_RX_DATA_END = 28 + SJA1000_BASE, /* OP:RO */
SJA1000_EFF_TX_DATA_END = 28 + SJA1000_BASE, /* OP:WO */
/* Acceptance Code Register */
SJA1000_ACR_BEGIN = 16 + SJA1000_BASE, /* SET:RW */
/* ................... ..... */
SJA1000_ACR_END = 19 + SJA1000_BASE, /* SET:RW */
/* Acceptance Mask Register */
SJA1000_AMR_BEGIN = 20 + SJA1000_BASE, /* SET:RW */
/* ................... ..... */
SJA1000_AMR_END = 23 + SJA1000_BASE, /* SET:RW */
/* reserved */
SJA1000_RSRV_3_BEGIN = 24 + SJA1000_BASE, /* SET:RO, read: 0 */
/* ................... ..... */
SJA1000_RSRV_3_END = 28 + SJA1000_BASE, /* SET:RO, read: 0 */
/* RX Message Counter */
SJA1000_RMC = 29 + SJA1000_BASE, /* RO */
SJA1000_RMC_MASK = 0x1F,
SJA1000_RMC_MASK_ZERO = 0xE0, /* always 0 */
/* RX Buffer Start Address, offset from RX_FIFO_BEGIN */
SJA1000_RBSA = 30 + SJA1000_BASE, /* OP:RO, SET:RW */
SJA1000_RBSA_MASK = 0x3F,
SJA1000_RBSA_MASK_ZERO = 0xC0, /* always 0 */
/* Clock Divider Register */
/* Some bits are writeable in reset mode only
(CAN mode, CBP, RXINTEN and clock off). */
SJA1000_CDR = 31 + SJA1000_BASE, /* RW */
SJA1000_CDR_CLOCK_DIVIDER = 0x07,
SJA1000_CDR_CLOCK_DIVIDER_2 = 0x00,
SJA1000_CDR_CLOCK_DIVIDER_4 = 0x01,
SJA1000_CDR_CLOCK_DIVIDER_6 = 0x02,
SJA1000_CDR_CLOCK_DIVIDER_8 = 0x03,
SJA1000_CDR_CLOCK_DIVIDER_10 = 0x04,
SJA1000_CDR_CLOCK_DIVIDER_12 = 0x05,
SJA1000_CDR_CLOCK_DIVIDER_14 = 0x06,
SJA1000_CDR_CLOCK_DIVIDER_1 = 0x07,
SJA1000_CDR_CLOCK_OFF = 0x08,
SJA1000_CDR_ZERO_MASK = 0x10, /* RO, always 0 */
SJA1000_CDR_RXINTEN = 0x20,
SJA1000_CDR_CBP = 0x40, /* bypass input comparator */
SJA1000_CDR_PELICAN_MODE = 0x80, /* 0=BasicCAN, 1=PeliCAN */
/* Internal RAM, RX FIFO */
SJA1000_RX_FIFO_BEGIN = 32 + SJA1000_BASE, /* OP:RO, SET:RW */
/* .................. ..... */
SJA1000_RX_FIFO_END = 95 + SJA1000_BASE, /* OP:RO, SET:RW */
/* Internal RAM, TX Buffer */
SJA1000_TXBUF_BEGIN = 96 + SJA1000_BASE, /* OP:RO, SET:RW */
/* ................. ..... */
SJA1000_TXBUF_END = 108 + SJA1000_BASE, /* OP:RO, SET:RW */
/* Internal RAM, Free */
SJA1000_RAM_FREE_BEGIN = 109 + SJA1000_BASE, /* OP:RO, SET:RW */
/* .................... ..... */
SJA1000_RAM_FREE_END = 111 + SJA1000_BASE, /* OP:RO, SET:RW */
/* Internal RW RAM aliases */
SJA1000_RAM_RW_BEGIN = SJA1000_RX_FIFO_BEGIN, /* OP:RO, SET:RW */
/* .................... ..... */
SJA1000_RAM_RW_END = SJA1000_RAM_FREE_END , /* OP:RO, SET:RW */
/* Internal RAM, Reserved */
SJA1000_RAM_RSRV_BEGIN = 112 + SJA1000_BASE, /* RO, read: 0 */
/* .................... ..... */
SJA1000_RAM_RSRV_END = 127 + SJA1000_BASE, /* RO, read: 0 */
SJA1000_RAM_SIZE = SJA1000_RAM_RSRV_END+1
};
#endif /* __XKCAN_SJA1000_H_ */
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