lvboqi.vhd

滤波器

-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM		"Quartus II"
-- VERSION		"Version 8.1 Build 163 10/28/2008 SJ Full Version"
-- CREATED ON		"Mon Apr 13 16:50:11 2009"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY lvboqi IS 
	PORT
	(
		a :  IN  STD_LOGIC;
		clk :  IN  STD_LOGIC;
		fa :  OUT  STD_LOGIC
	);
END lvboqi;

ARCHITECTURE bdf_type OF lvboqi IS 

SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
SIGNAL	DFF_1 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC;


BEGIN 



PROCESS(clk)
BEGIN
IF (RISING_EDGE(clk)) THEN
	DFF_1 <= a;
END IF;
END PROCESS;


SYNTHESIZED_WIRE_0 <= NOT(SYNTHESIZED_WIRE_2 OR SYNTHESIZED_WIRE_3 OR SYNTHESIZED_WIRE_4);


SYNTHESIZED_WIRE_1 <= SYNTHESIZED_WIRE_2 AND SYNTHESIZED_WIRE_4 AND SYNTHESIZED_WIRE_3;


PROCESS(clk)
BEGIN
IF (RISING_EDGE(clk)) THEN
	SYNTHESIZED_WIRE_3 <= DFF_1;
END IF;
END PROCESS;


PROCESS(clk)
BEGIN
IF (RISING_EDGE(clk)) THEN
	SYNTHESIZED_WIRE_4 <= SYNTHESIZED_WIRE_3;
END IF;
END PROCESS;


PROCESS(clk)
BEGIN
IF (RISING_EDGE(clk)) THEN
	SYNTHESIZED_WIRE_2 <= SYNTHESIZED_WIRE_4;
END IF;
END PROCESS;


PROCESS(clk)
VARIABLE synthesized_var_for_fa : STD_LOGIC;
BEGIN
IF (RISING_EDGE(clk)) THEN
	synthesized_var_for_fa := (NOT(synthesized_var_for_fa) AND SYNTHESIZED_WIRE_1) OR (synthesized_var_for_fa AND (NOT(SYNTHESIZED_WIRE_0)));
END IF;
	fa <= synthesized_var_for_fa;
END PROCESS;


END bdf_type;