clkc270.c

dm270 source code

            else
            if(clockSource==CLKC_PCLK)
                CLKC_FSET(CLKC, COSDS, 1);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_CCDC:
            if(clockSource==CLKC_SYSCLK)
                CLKC_FSET(CLKC, CCCDS, 1);
            else
            if(clockSource==CLKC_PCLK)
                CLKC_FSET(CLKC, CCCDS, 0);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_UART1:
            if(clockSource==CLKC_ARM_IN)
                CLKC_FSET(CLKC, CUA1S, 0);
            else
            if(clockSource==CLKC_PLL_IN)
                CLKC_FSET(CLKC, CUA1S, 1);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_UART0:
            if(clockSource==CLKC_ARM_IN)
                CLKC_FSET(CLKC, CUA0S, 0);
            else
            if(clockSource==CLKC_PLL_IN)
                CLKC_FSET(CLKC, CUA0S, 1);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_TMR3:
            if(clockSource==CLKC_ARM_IN)
                CLKC_FSET(CLKC, CTM3S, 0);
            else
            if(clockSource==CLKC_PLL_IN)
                CLKC_FSET(CLKC, CTM3S, 1);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_TMR2:
            if(clockSource==CLKC_ARM_IN)
                CLKC_FSET(CLKC, CTM2S, 0);
            else
            if(clockSource==CLKC_PLL_IN)
                CLKC_FSET(CLKC, CTM2S, 1);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_TMR1:
            if(clockSource==CLKC_ARM_IN)
                CLKC_FSET(CLKC, CTM1S, 0);
            else
            if(clockSource==CLKC_PLL_IN)
                CLKC_FSET(CLKC, CTM1S, 1);
            else
                status=E_INVALID_INPUT;
            break;

        case CLK_TMR0:
            if(clockSource==CLKC_ARM_IN)
                CLKC_FSET(CLKC, CTM0S, 0);
            else
            if(clockSource==CLKC_PLL_IN)
                CLKC_FSET(CLKC, CTM0S, 1);
            else
                status=E_INVALID_INPUT;
            break;

        default:
            status=E_INVALID_INPUT;
            break;
    }
    return status;
}

/**
    \brief Invert clock source for a specific module

    Clock source can be inverted for only specific modules. See register CLKC for details.

    \param moduleID  DM270 module ID (see CLKC_MOD_ID, for list of module ID's)
    \param invert    TRUE: invert clock, FALSE: do not invert clock

    \return if success, \c E_PASS, else error code
*/
STATUS CLKC_moduleInvertClock( CLKC_MOD_ID moduleID, BOOL invert) {
    STATUS status=E_PASS;

    switch(moduleID) {
        case CLK_CCDC:
            CLKC_FSET(CLKC, CCDIV, invert==TRUE ? 1 : 0 );
            break;
        case CLK_VENC:
            CLKC_FSET(CLKC, CENIV, invert==TRUE ? 1 : 0 );
            break;
        case CLK_MMC:
            CLKC_FSET(CLKC, CMCIV, invert==TRUE ? 1 : 0 );
            break;
        default:
            status=E_INVALID_INPUT;
            break;
    }
    return status;
}

/**
    \brief Put PLL A or PLL B in power down mode

    \param pwdnPllA     PLL A power down, TRUE:power down enable, FALSE: power down disable
    \param pwdnPllB     PLL B power down, TRUE:power down enable, FALSE: power down disable

    \return if success, \c E_PASS, else error code
*/
STATUS CLKC_pllPowerDown( BOOL pwdnPllA, BOOL pwdnPllB){
    CLKC_FSET( PLLA, PWRDN, pwdnPllA==TRUE ? 1 : 0);
    CLKC_FSET( PLLB, PWRDN, pwdnPllB==TRUE ? 1 : 0);
    return E_PASS;
}

/**
    \brief Bypass PLL for ARM, DSP, SDRAM, or AXL clock

    \param bypArm       ARM   Clock,  TRUE:bypass, FALSE: do not bypass
    \param bypDsp       DSP   Clock,  TRUE:bypass, FALSE: do not bypass
    \param bypSdram     SDRAM Clock,  TRUE:bypass, FALSE: do not bypass
    \param bypAxl       AXL   Clock,  TRUE:bypass, FALSE: do not bypass

    \return if success, \c E_PASS, else error code
*/
STATUS CLKC_pllBypass(BOOL bypArm, BOOL bypDsp, BOOL bypSdram, BOOL bypAxl) {
    CLKC_FSET( BYP, CMB, bypAxl==TRUE ? 1 : 0 );
    CLKC_FSET( BYP, CSB, bypSdram==TRUE ? 1 : 0 );
    CLKC_FSET( BYP, CDB, bypDsp==TRUE ? 1 : 0 );
    CLKC_FSET( BYP, CAB, bypArm==TRUE ? 1 : 0 );
    return E_PASS;
}

/**
    \brief Set MMC Function Clock Divisor value

    \code
        MMC Function Clock = ARM Clock / value
    \endcode

    \param value    MMC Clock div value, 1..256

    \return if success, \c E_PASS, else error code
*/
STATUS CLKC_setMMCClockDivValue( Uint16 value) {
    CLKC_RSET( MMCCLK, value-1);
    return E_PASS;
}

/**
    \brief  Enable or disable DM270 auto power down

    \param enable   TRUE: auto power down enable, \n FALSE: auto power down disable

    \return if success, \c E_PASS, else error code
*/
STATUS CLKC_autoPowerDownEnable( BOOL enable) {
    CLKC_FSET( LPCTL1, PDMD, enable==TRUE ? 1 :  0);
    return E_PASS;
}

/**
    \brief  Enable or disable M48XI clock

    \param enable   TRUE: Enable M48XI clock, FALSE: Disable M48XI clock

    \return if success, \c E_PASS, else error code
*/
STATUS CLKC_m48xiEnable( BOOL enable) {
    CLKC_FSET( LPCTL1, OSC48, enable==TRUE ? 0 : 1);
    return E_PASS;
}

/**
    \brief  Configure clock output signal

    Clock output 0 - GIO18, CLK OUT = CLK IN / (div), div=1..0x20000 \n
    Clock output 1 - GIO17, CLK OUT = CLK IN / (div), div=1..0x20000 \n
    Clock output 2 - GIO16, CLK OUT = CLK IN / (div), div=1..16

    \param  gioID               GIO terminal to use as clock out
    \param  clkoutConfig        Clock output configuration structure

    \return if success, \c E_PASS, else error code

    \see CLKOUT_ConfigData
*/
STATUS CLKC_setClockOutConfig( Uint16 gioID, CLKOUT_ConfigData *clkoutConfig){
    STATUS status=E_PASS;

    switch(gioID) {
        case GIO16:
            switch(clkoutConfig->clockSource) {
                case CLKC_ARM_IN:
                    CLKC_FSET(OSEL, O0SEL, 0);
                    break;
                case CLKC_DSP_IN:
                    CLKC_FSET(OSEL, O0SEL, 1);
                    break;
                case CLKC_SDRC_IN:
                    CLKC_FSET(OSEL, O0SEL, 2);
                    break;
                case CLKC_AXL_IN:
                    CLKC_FSET(OSEL, O0SEL, 3);
                    break;
                case CLKC_PLL_IN:
                    CLKC_FSET(OSEL, O0SEL, 4);
                    break;
                case CLKC_M48XI_IN:
                    CLKC_FSET(OSEL, O0SEL, 5);
                    break;
                default:
                    status=E_INVALID_INPUT;
            }
            CLKC_RSET( O0DIV, (clkoutConfig->div-1)/2);
            break;
        case GIO17:
            switch(clkoutConfig->clockSource) {
                case CLKC_ARM_IN:
                    CLKC_FSET(OSEL, O1SEL, 0);
                    break;
                case CLKC_DSP_IN:
                    CLKC_FSET(OSEL, O1SEL, 1);
                    break;
                case CLKC_SDRC_IN:
                    CLKC_FSET(OSEL, O1SEL, 2);
                    break;
                case CLKC_AXL_IN:
                    CLKC_FSET(OSEL, O1SEL, 3);
                    break;
                case CLKC_PLL_IN:
                    CLKC_FSET(OSEL, O1SEL, 4);
                    break;
                case CLKC_M48XI_IN:
                    CLKC_FSET(OSEL, O1SEL, 5);
                    break;
                default:
                    status=E_INVALID_INPUT;
            }
            CLKC_RSET( O1DIV, (clkoutConfig->div-1)/2);
            break;
        case GIO18:
            switch(clkoutConfig->clockSource) {
                case CLKC_ARM_IN:
                    CLKC_FSET(OSEL, O2SEL, 0);
                    break;
                case CLKC_DSP_IN:
                    CLKC_FSET(OSEL, O2SEL, 1);
                    break;
                case CLKC_SDRC_IN:
                    CLKC_FSET(OSEL, O2SEL, 2);
                    break;
                case CLKC_AXL_IN:
                    CLKC_FSET(OSEL, O2SEL, 3);
                    break;
                case CLKC_PLL_IN:
                    CLKC_FSET(OSEL, O2SEL, 4);
                    break;
                case CLKC_M48XI_IN:
                    CLKC_FSET(OSEL, O2SEL, 5);
                    break;
                default:
                    status=E_INVALID_INPUT;
            }
            CLKC_RSET( O0DIV, clkoutConfig->div-1);
            break;
        default:
            status=E_INVALID_INPUT;
            break;
    }
    return status;
}


/**
    \brief  Configure PWM output signal

    PWM output 0 - GIO 29   \n
    PWM output 1 - GIO 30

    \param  gioID               GIO terminal to use as PWM output
    \param  pwmConfig           PWM output configuration structure

    \return if success, \c E_PASS, else error code

    \see PWM_ConfigData
*/
STATUS CLKC_setPWMConfig( Uint16 gioID, PWM_ConfigData *pwmConfig) {
    STATUS status=E_PASS;

    switch(gioID) {
        case GIO29:
            CLKC_RSET(PWM0C, pwmConfig->cycleWidth);
            CLKC_RSET(PWM0H, pwmConfig->highPeriod);
            break;
        case GIO30:
            CLKC_RSET(PWM1C, pwmConfig->cycleWidth);
            CLKC_RSET(PWM1H, pwmConfig->highPeriod);
            break;
        default:
            status=E_INVALID_INPUT;
            break;
    }
    return status;
}

/**
    \brief  Returns module clock value for only ARM, DSP, SDRAM or AXL module

    \param moduleID  DM270 module ID (see CLKC_MOD_ID, for list of module ID's)

    \return Clock value in units of Hz
*/
Uint32 CLKC_getClockValue(CLKC_MOD_ID moduleID){
    Uint32 value;
    Uint8  pllA_M, pllA_N, pllB_M, pllB_N;

    pllA_M = CLKC_FGET( PLLA, PMA)+1;
    pllA_N = CLKC_FGET( PLLA, PNA)+1;

    pllB_M = CLKC_FGET( PLLB, PMB)+1;
    pllB_N = CLKC_FGET( PLLB, PNB)+1;

    value=27*1000*1000;

    switch(moduleID) {
        case CLK_ARM:
            if( CLKC_FGET( BYP, CAB ) == 1 ) {
                // pll is bypassed

            } else {
                if( CLKC_FGET(SEL, CARMS) == 0 ) {
                    // PLL A
                    value = (value*pllA_M)/pllA_N;
                } else {
                    // PLL B
                    value = (value*pllB_M)/pllB_N;
                }
            }
            switch( CLKC_FGET(DIV, CADIV) ) {
                case 1: value/=2; break;
                case 2: value/=3; break;
                case 3: value/=4; break;
            }
            break;

        case CLK_SDRC:
            if( CLKC_FGET( BYP, CSB ) == 1 ) {
                // pll is bypassed

            } else {
                if( CLKC_FGET(SEL, CSDRS) == 0 ) {
                    // PLL A
                    value = (value*pllA_M)/pllA_N;
                } else {
                    // PLL B
                    value = (value*pllB_M)/pllB_N;
                }
            }
            switch( CLKC_FGET(DIV, CSDIV) ) {
                case 1: value/=2; break;
                case 2: value/=3; break;
                case 3: value/=4; break;
            }
            break;

        case CLK_AXL:
            if( CLKC_FGET( BYP, CMB ) == 1 ) {
                // pll is bypassed

            } else {
                if( CLKC_FGET(SEL, CAXLS) == 0 ) {
                    // PLL A
                    value = (value*pllA_M)/pllA_N;
                } else {
                    // PLL B
                    value = (value*pllB_M)/pllB_N;
                }
            }
            switch( CLKC_FGET(DIV, CAXDIV) ) {
                case 1: value/=2; break;
                case 2: value/=3; break;
                case 3: value/=4; break;
            }
            break;

        case CLK_DSP:
            if( CLKC_FGET( BYP, CDB ) == 1 ) {
                // pll is bypassed

            } else {
                if( CLKC_FGET(SEL, CDSPS) == 0 ) {
                    // PLL A
                    value = (value*pllA_M)/pllA_N;
                } else {
                    // PLL B
                    value = (value*pllB_M)/pllB_N;
                }
            }
            switch( CLKC_FGET(DIV, CDDIV) ) {
                case 1: value/=2; break;
                case 2: value/=3; break;
                case 3: value/=4; break;
            }
            break;

        default:
            value=0;
            break;
    }
    return value;
}