📄 clkc270.c
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/*
DM270 ARM Evaluation Software
(c)Texas Instruments 2003
*/
/**
\file clkc270.c
\brief Clock Controller Related APIs
*/
#include <clkc270.h>
#include <gio270.h>
/**
\brief Configure clock controller
This routine initializes clock controller PLL A, PPL B, ARM, DSP, SDRAM, AXL clocks
\param clkcConfig Clock Controller configuration structure
\return if success, \c E_PASS, else error code
\see CLKC_ConfigData
*/
STATUS CLKC_setConfig( CLKC_ConfigData *clkcConfig){
STATUS status=E_PASS;
Uint16 value;
if(clkcConfig==NULL)
return E_INVALID_INPUT;
CLKC_RSET(BYP, 0x1111); // bypass PLL for ARM, DSP, AXL, SDRAM
// setup PLLA
value = CLKC_FMK(PLLA, PMA, clkcConfig->pllA_M-1) |
CLKC_FMK(PLLA, PNA, clkcConfig->pllA_N-1);
CLKC_RSET( PLLA, value );
// setup PLLB
value = CLKC_FMK(PLLB, PMB, clkcConfig->pllB_M-1) |
CLKC_FMK(PLLB, PNB, clkcConfig->pllB_N-1);
CLKC_RSET( PLLB, value);
// select ARM, DSP, AXL, SDRAM clock source as PLLA or PLLB
if(clkcConfig->axlPll==CLKC_PLLB_OUT)
CLKC_FSET( SEL, CAXLS, 1); // PLLB
else
CLKC_FSET( SEL, CAXLS, 0); // PLLA
if(clkcConfig->sdramPll==CLKC_PLLB_OUT)
CLKC_FSET( SEL, CSDRS, 1);
else
CLKC_FSET( SEL, CSDRS, 0);
if(clkcConfig->dspPll==CLKC_PLLB_OUT)
CLKC_FSET( SEL, CDSPS, 1);
else
CLKC_FSET( SEL, CDSPS, 0);
if(clkcConfig->armPll==CLKC_PLLB_OUT)
CLKC_FSET( SEL, CARMS, 1);
else
CLKC_FSET( SEL, CARMS, 0);
// set DIV value for ARM, DSP, SDRAM, AXL clock
CLKC_FSET( DIV, CAXDIV, clkcConfig->axlDiv-1);
CLKC_FSET( DIV, CSDIV, clkcConfig->sdramDiv-1);
CLKC_FSET( DIV, CDDIV, clkcConfig->dspDiv-1);
CLKC_FSET( DIV, CADIV, clkcConfig->armDiv-1);
{ // wait for PLLs to lock
Uint16 plla, pllb;
do {
plla = CLKC_RGET(PLLA) & 0x8000;
pllb = CLKC_RGET(PLLB) & 0x8000;
} while( plla == 0 || pllb == 0 );
}
// disable PLL bypass for ARM, DSP, AXL, SDRAM
CLKC_RSET(BYP, 0);
return status;
}
/**
\brief Enable clock to all DM270 modules
Make sure PLL A, PLLB as well as ARM, DSP, SDRAM, AXL clocks are initialized
by using CLKC_setConfig(), before calling this routine
\return if success, \c E_PASS, else error code
*/
STATUS CLKC_moduleEnableAll(){
CLKC_RSET( MOD0, 0x07FF);
CLKC_RSET( MOD1, 0x01FF);
CLKC_RSET( MOD2, 0x3FFF);
return E_PASS;
}
/**
\brief Enable or disable clock to a specific module
\param moduleID DM270 module ID (see CLKC_MOD_ID, for list of module ID's)
\param enable TRUE: enable, FALSE: disable
\return if success, \c E_PASS, else error code
*/
STATUS CLKC_moduleEnable( CLKC_MOD_ID moduleID, BOOL enable){
STATUS status=E_PASS;
switch(moduleID) {
case CLK_HPI:
CLKC_FSET(MOD0, CHPIB, enable==TRUE ? 1: 0);
break;
case CLK_DSP:
CLKC_FSET(MOD0, C5409, enable==TRUE ? 1: 0);
break;
case CLK_EHIF:
CLKC_FSET(MOD0, CEHIF, enable==TRUE ? 1: 0);
break;
case CLK_SDRC:
CLKC_FSET(MOD0, CSDRC, enable==TRUE ? 1: 0);
break;
case CLK_EMIF:
CLKC_FSET(MOD0, CEMIF, enable==TRUE ? 1: 0);
break;
case CLK_INTC:
CLKC_FSET(MOD0, CINTC, enable==TRUE ? 1: 0);
break;
case CLK_ATM:
CLKC_FSET(MOD0, CATM, enable==TRUE ? 1: 0);
break;
case CLK_AIM_DMA:
CLKC_FSET(MOD0, CADMAC, enable==TRUE ? 1: 0);
break;
case CLK_ICACHE:
CLKC_FSET(MOD0, CICA, enable==TRUE ? 1: 0);
break;
case CLK_BUSC:
CLKC_FSET(MOD0, CBUSC, enable==TRUE ? 1: 0);
break;
case CLK_ARM:
CLKC_FSET(MOD0, CACORE, enable==TRUE ? 1: 0);
break;
case CLK_IMG_BUF:
CLKC_FSET(MOD1, CIMG, enable==TRUE ? 1: 0);
break;
case CLK_IMX:
CLKC_FSET(MOD1, CIMX, enable==TRUE ? 1: 0);
break;
case CLK_VLCD:
CLKC_FSET(MOD1, CVLC, enable==TRUE ? 1: 0);
break;
case CLK_DAC:
CLKC_FSET(MOD1, CDAC, enable==TRUE ? 1: 0);
break;
case CLK_VENC:
CLKC_FSET(MOD1, CVENC, enable==TRUE ? 1: 0);
break;
case CLK_OSD:
CLKC_FSET(MOD1, COSD, enable==TRUE ? 1: 0);
break;
case CLK_PREV:
CLKC_FSET(MOD1, CPRV, enable==TRUE ? 1: 0);
break;
case CLK_H3A:
CLKC_FSET(MOD1, CH3A, enable==TRUE ? 1: 0);
break;
case CLK_CCDC:
CLKC_FSET(MOD1, CCCDC, enable==TRUE ? 1: 0);
break;
case CLK_I2C:
CLKC_FSET(MOD2, CI2C, enable==TRUE ? 1: 0);
break;
case CLK_MMC:
CLKC_FSET(MOD2, CMMC, enable==TRUE ? 1: 0);
break;
case CLK_SER1:
CLKC_FSET(MOD2, CSIF1, enable==TRUE ? 1: 0);
break;
case CLK_SER0:
CLKC_FSET(MOD2, CSIF0, enable==TRUE ? 1: 0);
break;
case CLK_UART1:
CLKC_FSET(MOD2, CUAT1, enable==TRUE ? 1: 0);
break;
case CLK_UART0:
CLKC_FSET(MOD2, CUAT0, enable==TRUE ? 1: 0);
break;
case CLK_USB:
CLKC_FSET(MOD2, CUSB, enable==TRUE ? 1: 0);
break;
case CLK_GIO:
CLKC_FSET(MOD2, CGIO, enable==TRUE ? 1: 0);
break;
case CLK_TMR3:
CLKC_FSET(MOD2, CTMR3, enable==TRUE ? 1: 0);
break;
case CLK_TMR2:
CLKC_FSET(MOD2, CTMR2, enable==TRUE ? 1: 0);
break;
case CLK_TMR1:
CLKC_FSET(MOD2, CTMR1, enable==TRUE ? 1: 0);
break;
case CLK_TMR0:
CLKC_FSET(MOD2, CTMR0, enable==TRUE ? 1: 0);
break;
case CLK_WDT:
CLKC_FSET(MOD2, CWDT, enable==TRUE ? 1: 0);
break;
default:
status=E_INVALID_INPUT;
break;
}
return status;
}
/**
\brief Check if clock to a specific module is enabled
\param moduleID DM270 module ID (see CLKC_MOD_ID, for list of module ID's)
\return TRUE: Clock is enabled, FALSE: Clock is disabled
*/
BOOL CLKC_isModuleEnabled( CLKC_MOD_ID moduleID){
Uint16 value;
switch(moduleID) {
case CLK_HPI:
value = CLKC_FGET(MOD0, CHPIB);
break;
case CLK_DSP:
value = CLKC_FGET(MOD0, C5409);
break;
case CLK_EHIF:
value = CLKC_FGET(MOD0, CEHIF);
break;
case CLK_SDRC:
value = CLKC_FGET(MOD0, CSDRC);
break;
case CLK_EMIF:
value = CLKC_FGET(MOD0, CEMIF);
break;
case CLK_INTC:
value = CLKC_FGET(MOD0, CINTC);
break;
case CLK_ATM:
value = CLKC_FGET(MOD0, CATM);
break;
case CLK_AIM_DMA:
value = CLKC_FGET(MOD0, CADMAC);
break;
case CLK_ICACHE:
value = CLKC_FGET(MOD0, CICA);
break;
case CLK_BUSC:
value = CLKC_FGET(MOD0, CBUSC);
break;
case CLK_ARM:
value = CLKC_FGET(MOD0, CACORE);
break;
case CLK_IMG_BUF:
value = CLKC_FGET(MOD1, CIMG);
break;
case CLK_IMX:
value = CLKC_FGET(MOD1, CIMX);
break;
case CLK_VLCD:
value = CLKC_FGET(MOD1, CVLC);
break;
case CLK_DAC:
value = CLKC_FGET(MOD1, CDAC);
break;
case CLK_VENC:
value = CLKC_FGET(MOD1, CVENC);
break;
case CLK_OSD:
value = CLKC_FGET(MOD1, COSD);
break;
case CLK_PREV:
value = CLKC_FGET(MOD1, CPRV);
break;
case CLK_H3A:
value = CLKC_FGET(MOD1, CH3A);
break;
case CLK_CCDC:
value = CLKC_FGET(MOD1, CCCDC);
break;
case CLK_I2C:
value = CLKC_FGET(MOD2, CI2C);
break;
case CLK_MMC:
value = CLKC_FGET(MOD2, CMMC);
break;
case CLK_SER1:
value = CLKC_FGET(MOD2, CSIF1);
break;
case CLK_SER0:
value = CLKC_FGET(MOD2, CSIF0);
break;
case CLK_UART1:
value = CLKC_FGET(MOD2, CUAT1);
break;
case CLK_UART0:
value = CLKC_FGET(MOD2, CUAT0);
break;
case CLK_USB:
value = CLKC_FGET(MOD2, CUSB);
break;
case CLK_GIO:
value = CLKC_FGET(MOD2, CGIO);
break;
case CLK_TMR3:
value = CLKC_FGET(MOD2, CTMR3);
break;
case CLK_TMR2:
value = CLKC_FGET(MOD2, CTMR2);
break;
case CLK_TMR1:
value = CLKC_FGET(MOD2, CTMR1);
break;
case CLK_TMR0:
value = CLKC_FGET(MOD2, CTMR0);
break;
case CLK_WDT:
value = CLKC_FGET(MOD2, CWDT);
break;
default:
value = FALSE;
break;
}
return (BOOL)value;
}
/**
\brief Select clock source for a specific module
Clock source can be selected for only specific modules. See registers CLKC, SEL for details.
\param moduleID DM270 module ID (see CLKC_MOD_ID, for list of module ID's)
\param clockSource Clock source. See registers CLKC, SEL for list of valid clock source for a particular module (see CLKC_SOURCE_ID for list of clock source ID's)
\return if success, \c E_PASS, else error code
*/
STATUS CLKC_moduleSelectClockSource( CLKC_MOD_ID moduleID, CLKC_SOURCE_ID clockSource){
STATUS status=E_PASS;
switch(moduleID) {
case CLK_DSP:
if(clockSource==CLKC_PLLB_OUT)
CLKC_FSET(SEL, CDSPS, 1);
else
if(clockSource==CLKC_PLLA_OUT)
CLKC_FSET(SEL, CDSPS, 0);
else
status=E_INVALID_INPUT;
break;
case CLK_SDRC:
if(clockSource==CLKC_PLLB_OUT)
CLKC_FSET(SEL, CSDRS, 1);
else
if(clockSource==CLKC_PLLA_OUT)
CLKC_FSET(SEL, CSDRS, 0);
else
status=E_INVALID_INPUT;
break;
case CLK_ARM:
if(clockSource==CLKC_PLLB_OUT)
CLKC_FSET(SEL, CARMS, 1);
else
if(clockSource==CLKC_PLLA_OUT)
CLKC_FSET(SEL, CARMS, 0);
else
status=E_INVALID_INPUT;
break;
case CLK_AXL:
if(clockSource==CLKC_PLLB_OUT)
CLKC_FSET(SEL, CAXLS, 1);
else
if(clockSource==CLKC_PLLA_OUT)
CLKC_FSET(SEL, CAXLS, 0);
else
status=E_INVALID_INPUT;
break;
case CLK_PLL_IN:
if(clockSource==CLKC_SYSCLK)
CLKC_FSET(CLKC, CFINS, 1);
else
if(clockSource==CLKC_MXI)
CLKC_FSET(CLKC, CFINS, 0);
else
status=E_INVALID_INPUT;
break;
case CLK_VENC:
if(clockSource==CLKC_PCLK) {
CLKC_FSET(CLKC, CENS1, 1);
}
else
if(clockSource==CLKC_SYSCLK) {
CLKC_FSET(CLKC, CENS1, 0);
CLKC_FSET(CLKC, CENS0, 1);
}
else
if(clockSource==CLKC_MXI) {
CLKC_FSET(CLKC, CENS1, 0);
CLKC_FSET(CLKC, CENS0, 0);
}
else
status=E_INVALID_INPUT;
break;
case CLK_OSD:
if(clockSource==CLKC_SYSCLK)
CLKC_FSET(CLKC, COSDS, 0);
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