clkc270.h

dm270 source code

/*
    DM270 ARM Evaluation Software

    (c)Texas Instruments 2003
*/

/** \defgroup CLKC Clock Controller */
/*@{*/

/** \file  clkc270.h
    \brief Clock Controller related APIs

    Also refer to DM270 register manual for details
*/


#ifndef __CLKC_270_H__
#define __CLKC_270_H__

#include <system/armsys270.h>

/**
    \brief Clock source ID. Clock controller clock sources for DM270 modules
*/
typedef enum {
	CLKC_PLLA_OUT   ,		///< PLL A clock output
	CLKC_PLLB_OUT   ,		///< PLL B clock output
	CLKC_PLL_IN     ,		///< PLL IN clock 
	CLKC_ARM_IN     ,		///< ARM Clock
	CLKC_DSP_IN     ,		///< DSP Clock
	CLKC_SDRC_IN    ,		///< SDRAM Clock
	CLKC_AXL_IN     ,		///< Accelerator Clock
	CLKC_M48XI_IN   ,		///< M48XI Clock
	CLKC_PCLK       ,		///< CCDC Pixel Clock
	CLKC_MXI        ,		///< MXI Clock
	CLKC_SYSCLK				///< System Clock
} CLKC_SOURCE_ID;

/**
    \brief Module ID. DM270 modules 
*/
typedef enum {
    CLK_HPI,        ///< HPIB clock
    CLK_DSP,        ///< DSP clock
    CLK_EHIF,       ///< External HOST interface clock
    CLK_SDRC,       ///< SDRAM controller clock
    CLK_EMIF,       ///< EMIF clock
    CLK_INTC,       ///< Interrupt contorller clock
    CLK_ATM,        ///< Address trace module clock
    CLK_AIM_DMA,    ///< ARM internal memory DMA clock
    CLK_ICACHE,     ///< I-cache clock
    CLK_BUSC,       ///< BUS controller clock
    CLK_ARM,        ///< ARM clock
    CLK_IMG_BUF,    ///< Image Buffer clock
    CLK_IMX,        ///< iMX clock
    CLK_VLCD,       ///< VLCD clock
    CLK_DAC,        ///< DAC clock
    CLK_VENC,       ///< Video encoder clock
    CLK_OSD,        ///< OSD clock
    CLK_PREV,       ///< Preview clock
    CLK_H3A,        ///< Hardware 3A clock
    CLK_CCDC,       ///< CCD controller clock
    CLK_I2C,        ///< I2C clock
    CLK_MMC,        ///< MMC/SD clock
    CLK_SER1,       ///< Serial interface 0 clock
    CLK_SER0,       ///< Serial interface 1 clock
    CLK_UART1,      ///< UART1 clock
    CLK_UART0,      ///< UART0 clock
    CLK_USB,        ///< USB clock
    CLK_GIO,        ///< GIO clock
    CLK_TMR3,       ///< Timer 3 clock
    CLK_TMR2,       ///< Timer 2 clock
    CLK_TMR1,       ///< Timer 1 clock
    CLK_TMR0,       ///< Timer 0 clock
    CLK_WDT,        ///< WDT clock
    CLK_AXL,        ///< Accelarator clock
    CLK_PLL_IN      ///< PLL input clock
} CLKC_MOD_ID;

/**
    \brief Clock controller PLL configuration

    Refer to DM270 Register Manual for details of each field

    \code
        PLLOUT = (PLLIN*M)/N
    \endcode
*/
typedef struct {
    Uchar pllA_M;       ///<  M divider for PLLA, M=1..16
    Uchar pllA_N;       ///<  N divider for PPLA, N=1..8
    Uchar pllB_M;       ///<  M divider for PPLA, M=1..16
    Uchar pllB_N;       ///<  N divider for PPLA, N=1..8

    CLKC_SOURCE_ID axlPll;       ///<  CLKC_PLLA_OUT or CLKC_PLLB_OUT
    CLKC_SOURCE_ID sdramPll;     ///<  CLKC_PLLA_OUT or CLKC_PLLB_OUT
    CLKC_SOURCE_ID armPll;       ///<  CLKC_PLLA_OUT or CLKC_PLLB_OUT
    CLKC_SOURCE_ID dspPll;       ///<  CLKC_PLLA_OUT or CLKC_PLLB_OUT

    Uchar axlDiv;       ///<  AXL Clock divide value, 0: DIV 1, 1: DIV 2, 2: DIV 4, 3: DIV 8
    Uchar sdramDiv;     ///<  SDRAM Clock divide value, 0: DIV 1, 1: DIV 2, 2: DIV 4, 3: DIV 8
    Uchar armDiv;       ///<  ARM Clock divide value, 0: DIV 1, 1: DIV 2, 2: DIV 4, 3: DIV 8
    Uchar dspDiv;       ///<  DSP Clock divide value, 0: DIV 1, 1: DIV 2, 2: DIV 4, 3: DIV 8
} CLKC_ConfigData;

/**
    \brief Clock output terminal configuration parameters

    Clock output 0 - GIO18, CLK OUT = CLK IN / (div), div=1..0x20000 \n
    Clock output 1 - GIO17, CLK OUT = CLK IN / (div), div=1..0x20000 \n
    Clock output 2 - GIO16, CLK OUT = CLK IN / (div), div=1..16

	Make sure GIO18, GIO17, GIO16 is configured for alternate function use, using GIO_setConfig(), before using this feature
*/
typedef struct {
    CLKC_SOURCE_ID clockSource;     ///< CLKC_ARM_IN, CLKC_DSP_IN, CLKC_SDRC_IN, CLKC_AXL_IN, CLKC_PLL_IN, CLKC_M48XI_IN
    Uint32 div;						///< divide value for clock output 0,1,2
}  CLKOUT_ConfigData;

/**
    \brief PWM output configuration parameters

    PWM output 0 - GIO 29   \n
    PWM output 1 - GIO 30

	Make sure GIO29, GIO30 is configured for alternate function use, using GIO_setConfig(), before using this feature
*/
typedef struct {
    Uint16 cycleWidth;      ///< PWM cycle width 0..0xFFFF in units of PLL IN cycles
    Uint16 highPeriod;      ///< PWM high level width 0..0xFFFF in units of PLL IN cycles
} PWM_ConfigData;


STATUS CLKC_setConfig( CLKC_ConfigData *clkcConfig);
STATUS CLKC_moduleEnableAll();
STATUS CLKC_moduleEnable( CLKC_MOD_ID moduleID, BOOL enable);
BOOL   CLKC_isModuleEnabled( CLKC_MOD_ID moduleID);
STATUS CLKC_moduleSelectClockSource( CLKC_MOD_ID moduleID, CLKC_SOURCE_ID clockSource);
STATUS CLKC_moduleInvertClock( CLKC_MOD_ID moduleID, BOOL invert) ;
STATUS CLKC_pllPowerDown( BOOL pwdnPllA, BOOL pwdnPllB);
STATUS CLKC_pllBypass(BOOL bypArm, BOOL bypDsp, BOOL bypSdram, BOOL bypAxl) ;
STATUS CLKC_setMMCClockDivValue( Uint16 value) ;
STATUS CLKC_autoPowerDownEnable( BOOL enable) ;
STATUS CLKC_m48xiEnable( BOOL enable) ;
STATUS CLKC_setClockOutConfig( Uint16 gioID, CLKOUT_ConfigData *clkoutConfig);
STATUS CLKC_setPWMConfig( Uint16 gioID, PWM_ConfigData *pwmConfig) ;
Uint32 CLKC_getClockValue(CLKC_MOD_ID moduleID);

#endif /*   __CLKC_270_H__   */

/*@}*/