ccdc270.h

dm270 source code

/*
    DM270 ARM Evaluation Software

    (c)Texas Instruments 2003
*/

/** \defgroup CCDC CCD Controller */
/*@{*/

/** \file  ccdc270.h
    \brief CCD Controller related APIs

    Also refer to DM270 register manual for details
*/


#ifndef __CCDC_270_H__
#define __CCDC_270_H__

#include <system/armsys270.h>

#define CCDC_RAW_DATA       0
#define CCDC_YUV16_DATA     1
#define CCDC_YUV8_DATA      2

#define CCDC_COL_R          0
#define CCDC_COL_Gr         1
#define CCDC_COL_Gb         2
#define CCDC_COL_B          3


/**
    \brief CCDC Configuration parameters
*/
typedef struct {
    Uint8 dataInputMode;            ///< Data input mode, 0:CCDC_RAW_DATA, 1:CCDC_YUV16_DATA, 2:CCDC_YUV8_DATA
    Uint8 ccdDataWidth;             ///< Input pixel width in units of bits, valid data widths are 8..14
    BOOL  ccdModeInterlace;         ///< CCD reading method, TRUE: Interlaced mode , FALSE: Progressive mode
    BOOL  dataPolarityInverse;      ///< Data polarity, TRUE: Inverse , FALSE: Non-inverse
    BOOL  useWen;                   ///< WEN signal, TRUE: Use WEN signal, FALSE: Dont use WEN signal
    BOOL  fieldIdPolarityNegative;  ///< Field ID polarity, TRUE: Negative, FALSE: Positve
    BOOL  hdPolarityNegative;       ///< HD polarity, TRUE: Negative, FALSE: Positive
    BOOL  vdPolarityNegative;       ///< VD polarity, TRUE: Negative, FALSE: Positive
    BOOL  fieldIdDirOutput;         ///< Field ID direction, TRUE: Output, FALSE: Input
    BOOL  hdvdDirOutput;            ///< HD/VD direction, TRUE: Output, FALSE: Input
} CCDC_ConfigData;

/**
    \brief CCD Controller Mode Configuration parameters

    Refer to CCDC section in DM270 register manual for details
*/
typedef struct {
    Uint16 hdWidth;                 ///< HD width, 1..4096, units: pixel clock cycles
    Uint16 vdWidth;                 ///< VD Width, 1..4096, units: lines
    Uint16 pixelsPerLine;           ///< Pixels per line, 1..65536
    Uint16 linesPerFrame;           ///< Lines per frames, 1..32768
    Uint16 startPixelH;             ///< Start pixel horizontal, 0..4095
    Uint16 numPixelH;               ///< Number of horizontal pixels, 1..4096
    Uint16 startLineVEvenField;     ///< Start line vertical, Even Field, 0..4095
    Uint16 startLineVOddField;      ///< Start line vertical, Odd  Field, 0..4095
    Uint16 numPixelV;               ///< Number of vertical lines, 1..4096
    Uint8  cullPatternHEvenLine;    ///< Cull pattern horizontal, even line, see register CULH
    Uint8  cullPatternHOddLine;     ///< Cull pattern horizontal, odd  line, see register CULH
    Uint8  cullPatternV;            ///< Cull pattern vertical, see register CULV
    Uint16 reg_sdofst;              ///< Value to be set in Register SDOFST (0x3071c)
    Uint16 sdramLineOffset;         ///< SDRAM line offset, in units of bytes, must be multiple of 32bytes
    char   *sdramAddress;           ///< Raw data output address, absolute SDRAM address, must be 32byte aligned
    Uint16 sdramStorageMode;        ///< SDRAM storage mode, 0: 16bit/pixel, 1: 8bit/pixel
    Uint16 vdint0Interval;          ///< VD0 interrupt timing, 0..4095 lines from start of VD
    Uint16 vdint1Interval;          ///< VD1 interrupt timing, 0..4095 lines from start of VD
    BOOL   shutterControlEnable;    ///< Shutter Control, TRUE: Enable, FALSE: Disable
} CCDC_ModeData;

/**
    \brief CCD Controller data processing related configuration parameters

    Refer to CCDC section in DM270 register manual for details

    \see \ref FIXED_POINT_NOTATION
*/
typedef struct {
    BOOL   hlpfEnable;              ///< Horizontal low pass filter, TRUE: Enable, FALSE: Disable
    BOOL   clampEnable;             ///< Clamp enable, TRUE: Enable, FALSE: Disable
    Uint8  clampPixel;              ///< Number of pixels for clamp detection, 0: 8pixels, 1:16pixels
    Uint8  clampLine;               ///< Number of lines used for clamp detection, 0:8lines, 1:16lines
    Uint16 clampStart;              ///< Clamp detection start position in units of pixels from start of HD, 0..4095
    Uint16 dcsubValue;              ///< DC value subtracted when clampEnable = FALSE, 0..16383
    Uint8  colPatFld0EvenEven;      ///< Color Pattern, Field 0, Even pixel, Even line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld0OddEven;       ///< Color Pattern, Field 0, Odd  pixel, Even line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld0EvenOdd;       ///< Color Pattern, Field 0, Even pixel, Odd  line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld0OddOdd;        ///< Color Pattern, Field 0, Odd  pixel, Odd  line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld1EvenEven;      ///< Color Pattern, Field 1, Even pixel, Even line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld1OddEven;       ///< Color Pattern, Field 1, Odd  pixel, Even line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld1EvenOdd;       ///< Color Pattern, Field 1, Even pixel, Odd  line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Uint8  colPatFld1OddOdd;        ///< Color Pattern, Field 1, Odd  pixel, Odd  line, 0: CCDC_COL_R, 1: CCDC_COL_Gr, 2: CCDC_COL_Gb, 3:CCDC_COL_B
    Int8   offsetR;                 ///< R offset, -128..127
    Int8   offsetGr;                ///< Gr offset, -128..127
    Int8   offsetGb;                ///< Gb offset, -128..127
    Int8   offsetB;                 ///< B offset, -128..127
    BOOL   medianFilterEnable;      ///< Median filter enable, TRUE: Enable, FALSE: Disable
    Uint16 medianFilterThreshold;   ///< Median filter threshold, 0..8191
    Uint16 gain;                    ///< Gain, 0..(7.9921875), Format U11Q8
    Uint16 offset;                  ///< Offset, 0..1023
    Uint16 outputThreshold;         ///< Output threshold, 0..0x3FFF
    Uint16 outputClip;              ///< Output clip, 0..0x3FFF
    Uint16 gammaInputWidth;         ///< Input data width to A-law is selected, 0:13-4bit, 1:12-3bit, 2:11-2bit, 3:10-1bit, 4:9-0bit
    BOOL   gammaH3AEnable;          ///< A-law table for H3A, TRUE: Enable, FALSE: Disable
    BOOL   gammaCCDCEnable;         ///< A-law table for CCDC, TRUE: Enable, FALSE: Disable
} CCDC_ProcessingData;

STATUS CCDC_setConfig( CCDC_ConfigData *ccdcConfig );
STATUS CCDC_setMode( CCDC_ModeData *ccdcMode);
STATUS CCDC_setProcessing( CCDC_ProcessingData *ccdcProcessing);
STATUS CCDC_enable( BOOL hdvdEnable, BOOL sdrWrEnable);
STATUS CCDC_setSdramAddress( char *sdramAddress);
STATUS CCDC_setVDINTInterval( Uint8 vdintID, Uint16 interval);
STATUS CCDC_rec656Enable( BOOL enable, BOOL errorCorrectionEnable);
STATUS CCDC_miscControl( Uint16 ctrlValue );


#endif /*   __CCDC_270_H__   */

/*@}*/