emif270.h

dm270 source code

/*
    DM270 ARM Evaluation Software

    (c)Texas Instruments 2003
*/

/** \defgroup EMIF External Memory Interface */
/*@{*/

/** \file  emif270.h
    \brief External Memory Interface related APIs

    Also refer to DM270 register manual for details
*/


#ifndef _EMIF270_H_
#define _EMIF270_H_

#include <system/armsys270.h>

/**
	\brief Endianess swapping mode during DMA transfer
*/
typedef enum {
  EMIF_NO_SWAP,			///< No Swap in transfer
  EMIF_BYTE_SWAP,		///< Byte Swap in transfer
  EMIF_WORD_SWAP,		///< Word Swap in transfer
  EMIF_BYTE_WORD_SWAP	///< Byte and Word Swap in transfer
} EMIF_SWAP_MODE;

/**
	\brief DMA Transfer Device (Source/Destination)
*/
typedef enum {
  EMIF_DMA_CS0,			///< DMA Transfer Device CS0
  EMIF_DMA_CS1,			///< DMA Transfer Device CS1
  EMIF_DMA_CS2,			///< DMA Transfer Device CS2
  EMIF_DMA_CS3,			///< DMA Transfer Device CS3
  EMIF_DMA_CS4,			///< DMA Transfer Device CS4
  EMIF_DMA_SDRAM,		///< DMA Transfer Device SDRAM
  EMIF_DMA_AIM			///< DMA Transfer Device ARM Internal Memory
} EMIF_DMA_DEVICE;
  
/**
	\brief Memory Region ID for EMIF
*/  
typedef enum {
  EMIF_CS0,			///< CS0 region
  EMIF_CS1,			///< CS1 region
  EMIF_CS2,			///< CS2 region
  EMIF_CS3,			///< CS3 region
  EMIF_CS4,			///< CS4 region
  EMIF_SDRAM		///< SDRAM region
}EMIF_ID;

/**
	\brief Module ID for EMIF access by different modules
*/
typedef enum {
  EMIF_ARM,			///< ARM access EMIF
  EMIF_DMA,			///< DMA access EMIF
  EMIF_IMG_BUF,		///< Image Buffer access EMIF
  EMIF_DSP			///< DSP(HPIB) access EMIF
}EMIF_MOD_ID;

/**
	\brief Priority for EMIF access
*/
typedef enum {
  EMIF_PRIORITY_1,	///< Priority 1:Highest Priority
  EMIF_PRIORITY_2,	///< Priority 2
  EMIF_PRIORITY_3,	///< Priority 3
  EMIF_PRIORITY_4	///< Priority 4:Lowest Priority
}EMIF_PRIORITY;  

/**
	\brief Polarity of Chip Enable for CS4 only
*/
typedef enum {
  EMIF_CE_LOW,		///< Chip Enable is Low Active
  EMIF_CE_HIGH		///< Chip Enable is High Active
} EMIF_CE_POLARITY;  

/**
	\brief EMIF bus width for CS3 and CS4 only
*/
typedef enum {
  EMIF_BUSWID_8,	///< 8 bits of bus access for EMIF
  EMIF_BUSWID_16	///< 16 bits of bus access for EMIF
} EMIF_BUS_WIDTH;  
  
/**
	\brief EMIF Configuration parameters
*/  
typedef struct {
  Uint16 oeWidth;		///< Width of Output Enable(in clock cycles) ranging from 1 to 16 for CS0, CS2, CS3, CS4 and 1 to 32 for CS1 
  Uint16 weWidth;		///< Width of Write Enable(in clock cycles) ranging from 1 to 16 for CS0, CS2, CS3, CS4 and 1 to 32 for CS1		
  Uint16 ceWidth;		///< Width of Chip Enable(in clock cycles) ranging from 1 to 16 for CS0, CS3, CS4 and 1 to 32 for CS1 and "Don't Care" for CS2
  Uint16 cycleWidth;	///< Width of Cycle(in clock cycles) ranging from 2 to 16 for CS0, CS2, CS3, CS4 and 2 to 32 for CS1
  Uint16 idleWidth;		///< Width of IDLE state(in clock cycles) ranging from 0 to 3 for CS0, CS1, CS2, CS3, CS4
  Uint16 oeSetupWidth;	///< Width of Output Enable Setup(in clock cycles) ranging from 1 to 16 for CS0, CS1, CS2, CS3, CS4
  Uint16 weSetupWidth;	///< Width of Write Enable Setup(in clock cycles) ranging from 1 to 16 for CS0, CS1, CS2, CS3, CS4
  Uint16 ceSetupWidth;	///< Width of Chip Enable Setup(in clock cycles) ranging from 0 to 15 for CS0, CS1, CS3, CS4 and Read Cycle Setup ranging from 3 to 18 for CS2
  EMIF_BUS_WIDTH busWidth;		///< Bus Width, EMIF_BUSWID_8:8 bits of bus width,  EMIF_BUSWID_16:16 bits of bus width, Applicable only for CS3 and CS4
  EMIF_CE_POLARITY cePolarity;	///< Chip Enable Polarity, EMIF_CE_LOW:For CE Low Active, EMIF_CE_HIGH: For CE High Active, Applicable for CS4 only 
} EMIF_ConfigData;

/**
	\brief EMIF Configuration parameters
*/  
typedef struct {
  Uint32 *source;			///< source Address offset from base address of source device, Has to be 4 byte aligned
  BOOL srcAddrFixed;		///< Auto Increment, TRUE:No auto increment in source address, FALSE:Auto increment in source address
  Uint32 *destination;		///< destination Address offset from base address of destination device, Has to be 4 byte aligned
  BOOL destAddrFixed;		///< Auto Increment, TRUE:No auto increment in destination address, FALSE:Auto increment in destination address
  Uint32 dmaSize;			///< Size of transfer in bytes, Must be a multiple of 4 bytes
  EMIF_DMA_DEVICE srcDev;	///< Source device for DMA
  EMIF_DMA_DEVICE destDev;	///< Destination device for DMA		
  EMIF_SWAP_MODE swapMode;	///< Endianess Swap Mode, EMIF_NO_SWAP, EMIF_BYTE_SWAP, EMIF_WORD_SWAP, EMIF_BYTE_WORD_SWAP    
} EMIF_DMAConfigData;


/*----- Function prototypes -----*/
STATUS EMIF_setConfig(EMIF_ID emidID, EMIF_ConfigData *emifConfig );
STATUS EMIF_setPriority(EMIF_MOD_ID moduleID, EMIF_PRIORITY emifPriority );
STATUS EMIF_setDmaConfig(EMIF_DMAConfigData *emifDmaConfig);
STATUS EMIF_updateSrcAddr(Uint32 * source);
STATUS EMIF_updateDestAddr(Uint32 * destination);
STATUS EMIF_dmaStart();
STATUS EMIF_dmaWait(Uint32 timeOut);
STATUS EMIF_setStartAddress(EMIF_ID emifID, Uint32 address);
Uint32 EMIF_getStartAddress(EMIF_ID emifID);
STATUS EMIF_setImgDspConfig(BOOL imgOrDspTransfer, EMIF_ID emifID, Uint32 address);


#endif /* _EMIF270_H_ */


/*@}*/