sdrc270.h

dm270 source code

/*
    DM270 ARM Evaluation Software

    (c)Texas Instruments 2003
*/

/** \defgroup SDRC SDRAM Controller */
/*@{*/

/** \file  sdrc270.h
    \brief SDRAM Controller related APIs

    Also refer to DM270 register manual for details
*/


#ifndef _SDRC270_H_
#define _SDRC270_H_

#include <system/armsys270.h>

/*---------------------------------------------------*/
/*----- Constant definitions for SDRC registers -----*/
/*----- MODESET register -----*/

extern Uint16 *SDRC_Buffer16;

/**
	\brief Control Commands for SDRAM
*/
typedef enum {
SDRC_CTRLSEL_NOP = 0x00,	///< No Operation
SDRC_CTRLSEL_MSR = 0x01,	///< SDRAM Mode Setting
SDRC_CTRLSEL_PREA = 0x02,	///< All Banks Pre Charge
SDRC_CTRLSEL_REF  = 0x04,	///< Auto Refresh Command
SDRC_CTRLSEL_SELF  = 0x08,	///< Self Refresh Mode
SDRC_CTRLSEL_SELFC = 0x10,	///< Self Refresh Mode and Powerdown mode cleared
SDRC_CTRLSEL_PDN = 0x20		///< Power Down mode
} SDRC_CTRL_COMMAND;

/**
	\brief CAS LAtency for SDRAM access
*/
typedef enum {
  SDRC_CASLATENCY_2,	///< CAS Latency of 2 cycles
  SDRC_CASLATENCY_3		///< CAS Latency of 3 cycles
} SDRC_CAS_LATENCY;  

/**
	\brief Number of Banks in SDRAM
*/
typedef enum {
  SDRC_BANKSELECT_2,	///< 2 Banks SDRAM	
  SDRC_BANKSELECT_4		///< 4 Banks SDRAM
} SDRC_BANK_SELECT;  

/**
	\brief SDRAM Memory Type
*/
typedef enum {
  SDRC_MEMTYPE_2KX256W,	///< Memory Type 2K x 256 Words
  SDRC_MEMTYPE_4KX256W,	///< Memory Type 4K x 256 Words
  SDRC_MEMTYPE_4KX512W,	///< Memory Type 4K x 512 Words
  SDRC_MEMTYPE_8KX512W	///< Memory Type 8K x 512 Words
} SDRC_MEMORY_TYPE;  

/**
	\brief DQM Select
*/
typedef enum {
  SDRC_DQMCTRL_NORMAL,	///< Normal DQM
  SDRC_DQMCTRL_FORCE	///< Forcibly set DQM to 1
} SDRC_DQM_CONTROL;  

/**
	\brief TRLD cycles for SDRAM access
*/
typedef enum {
  SDRC_TRDL_1CYCLE,		///< TRDL of 1 cycles
  SDRC_TRDL_2CYCLE		///< TRDL of 2 cycles
} SDRC_TRDL_SELECT;  

/**
	\brief TRCD cycles for SDRAM access
*/
typedef enum {
  SDRC_TRCD_2CYCLE,		///< TRCD of 2 cycles
  SDRC_TRCD_3CYCLE		///< TRCD of 3 cycles
}SDRC_TRCD_SELECT;  

/**
	\brief SDRAM Access Bus width
*/
typedef enum {
  SDRC_BUSWID_32,		///< 32 bits bus width
  SDRC_BUSWID_16		///< 16 bits bus width 
} SDRC_BUS_WIDTH;

/**
	\brief SDRAM Power States
*/
typedef enum {
  SDRC_POWER_DOWN,		///< SDRAM Power Down State
  SDRC_POWER_UP			///< SDRAM Power UP State
} SDRC_STATE;

/**
	\brief Channel ID for EM DMA Channels
*/
typedef enum {
  SDRC_DMACH_1,			///< SDRAM EMIF DMA Channel 1
  SDRC_DMACH_2			///< SDRAM EMIF DMA Channel 2
} SDRC_DMA_CH;
  
/**
	\brief Module ID for peripherals sharing the EM DMA Channels
*/  
typedef enum {
  SDRC_DMASEL_EMIF = 0,	///< DMA Channel for EXBC
  SDRC_DMASEL_SPI,		///< DMA Channel for SPI
  SDRC_DMASEL_USB,		///< DMA Channel for USB
  SDRC_DMASEL_MMCSD,	///< DMA Channel for MMC/SD/MS
  SDRC_DMASEL_DSP		///< DMA Channel for DSP (HPIB)
} SDRC_DMA_MOD_ID;

/**
	\brief Module ID for peripherals accessing SDRAM
*/
typedef enum {
  SDRC_CCDC,			///< CCDC DMA Channel
  SDRC_PREV,			///< PREVIEW DMA Channel
  SDRC_H3A,				///< Hardware 3A DMA Channel
  SDRC_OSD,				///< OSD DMA Channel
  SDRC_EXT_HOST,		///< External Host
  SDRC_ARM_CPU,			///< ARM CPU Random request
  SDRC_EM2,				///< EMIF DMA Channel 2
  SDRC_EM1,				///< EMIF DMA Channel 1
  SDRC_IMG_BUF,			///< DSP Image Buffer DMA Channel
  SDRC_AUTO_REF			///< SDRAM Auto Referesh
}SDRC_MOD_ID;

/**
	\brief Priority for SDRAM access
*/
typedef enum {
  SDRC_PRIORITY_1 = 0x200,	///< Priority 1:Highest Priority
  SDRC_PRIORITY_2 = 0x100,	///< Priority 2
  SDRC_PRIORITY_3 = 0x080,	///< Priority 3
  SDRC_PRIORITY_4 = 0x040,	///< Priority 4
  SDRC_PRIORITY_5 = 0x020,	///< Priority 5
  SDRC_PRIORITY_6 = 0x010,	///< Priority 6
  SDRC_PRIORITY_7 = 0x008,	///< Priority 7
  SDRC_PRIORITY_8 = 0x004,	///< Priority 8
  SDRC_PRIORITY_9 = 0x002,	///< Priority 9
  SDRC_PRIORITY_10 = 0x001	///< Priority 10:Lowest Priority
}SDRC_PRIORITY;  

/**
	\brief SDRAM Burst Access Ports
*/
typedef enum {
  SDRC_NO_PORT = 0,			///< FIFO access function OFF
  SDRC_PREV_PORT,			///< Preview Engine Port
  SDRC_3A_PORT,				///< 3A Engine Port
  SDRC_EXT_PORT				///< External CPU I/F PORT
} SDRC_PORT;  

/**
	\brief SDRAM Burst Write Modes
*/
typedef enum {
  SDRC_WRITE_ALL = 0,		///< WRITE ALL Mode for burst write to SDRAM
  SDRC_WRITE_MODIFIED		///< WRITE MODIFIED data only
} SDRC_WRITE_MODE;  
  
/**
	\brief SDRAM Controller Configuration parameters
*/  
typedef struct {
  SDRC_TRDL_SELECT  trdlSelect;			///< tRDL Select, SDRC_TRDL_1CYCLE:1 cycle, SDRC_TRDL_2CYCLE:2 cycles
  SDRC_BUS_WIDTH  busWidth;             ///< SDRAM Bus Width, SDRC_BUSWID_16:16-bits, SDRC_BUSWID_32:32-bits
  SDRC_TRCD_SELECT trcdSelect;			///< tRCD Select, SDRC_TRCD_2CYCLE:2 cycle, SDRC_TRDC_3CYCLE:3 cycles
  SDRC_BANK_SELECT bankSelect;			///< SDRAM Banks, SDRC_BANKSELECT_2:2 banks, SDRC_BANKSELECT_4:4 banks
  SDRC_CAS_LATENCY casLatency;			///< CAS Latency, SDRC_CASLATENCY_2:2 cycles, SDRC_CASLATENCY_3:3 cycles
  SDRC_MEMORY_TYPE memoryType;			///< SDRAM Memory Type, SDRC_MEMTYPE_2KX256W:2k x 256 words, SDRC_MEMTYPE_4KX256W:4k x 256 words, SDRC_MEMTYPE_4KX512W:4k x 512 words, SDRC_MEMTYPE_8KX512W:8k x 512 words
  SDRC_DQM_CONTROL dqmControl;			///< SDRAM DQM Control, SDRC_DQMCTRL_NORMAL:Normal, SDRC_DQMCTRL_FORCE:Forcibly sets DQM signal to 1
  BOOL  autoPowerDownMode;		///< SDRAM Auto Power Down Mode, TRUE:Enabled, FALSE:Disabled
  BOOL  autoRefresh;			///< SDRAM Auto Referesh Enable, TRUE:Enabled, FALSE:Disabled
  Uint16  autoRefreshInterval;	///< Interval of auto refresh, Interval is (REFC + 1) x 8 SDRAM clocks
  Uint16 *setupSequence;		///< Pointer to array of setup sequence codes
  Uint16  numSequenceSteps;		///< Number of items in setup sequence
} SDRC_ConfigData;



/*----- Function prototypes -----*/
STATUS SDRC_setConfig( SDRC_ConfigData *sdrcConfig );
STATUS SDRC_setPriority( SDRC_MOD_ID moduleID, SDRC_PRIORITY sdrcPriority );
STATUS SDRC_selectDmaChannel( SDRC_DMA_MOD_ID dmaModuleID, SDRC_DMA_CH dmaChannelID );
STATUS SDRC_clearBufferData();
STATUS SDRC_enableUserDefinedPriority(BOOL enable);
STATUS SDRC_burstRead(Uint32 *sdramAddress, Uint32 *dataAddress, Uint32 dataSize, SDRC_PORT portID);
STATUS SDRC_burstWrite(Uint32 *sdramAddress, Uint32 *dataAddress, Uint32 dataSize, SDRC_PORT portID, SDRC_WRITE_MODE writeMode);

#endif /* _SDRC270_H_ */


/*@}*/