csl_intchal_270.h

dm270 source code

#define _INTC_EINT1_EXT0_MASK			(_INTC_EINT1_EXT0_MK(0x0001u))
#define _INTC_EINT1_EXT0_CLR			(~(_INTC_EINT1_EXT0_MASK))

#define _INTC_EINT1_MMCSD1_SHIFT		(2)
#define _INTC_EINT1_MMCSD1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT1_MMCSD1_SHIFT)
#define _INTC_EINT1_MMCSD1_MASK			(_INTC_EINT1_MMCSD1_MK(0x0001u))
#define _INTC_EINT1_MMCSD1_CLR			(~(_INTC_EINT1_MMCSD1_MASK))

#define _INTC_EINT1_MMCSD0_SHIFT		(1)
#define _INTC_EINT1_MMCSD0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT1_MMCSD0_SHIFT)
#define _INTC_EINT1_MMCSD0_MASK			(_INTC_EINT1_MMCSD0_MK(0x0001u))
#define _INTC_EINT1_MMCSD0_CLR			(~(_INTC_EINT1_MMCSD0_MASK))

#define _INTC_EINT1_MTC1_SHIFT		(0)
#define _INTC_EINT1_MTC1_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_EINT1_MTC1_MASK			(_INTC_EINT1_MTC1_MK(0x0001u))
#define _INTC_EINT1_MTC1_CLR			(~(_INTC_EINT1_MTC1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC EINT2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_EINT2_GET()			_REG_GET(_INTC_EINT2_ADDR)
#define _INTC_EINT2_SET(Val)			_REG_SET(_INTC_EINT2_ADDR, Val)
#define _INTC_EINT2_AOI(AND,OR,INV)		_REG_AOI(_INTC_EINT2_ADDR,AND,OR,INV)
#define _INTC_EINT2_FGET(Field)			_FIELD_GET(_INTC_EINT2_ADDR, _INTC_EINT2_##Field##)
#define _INTC_EINT2_FSET(Field, Val)		_FIELD_SET(_INTC_EINT2_ADDR, _INTC_EINT2_##Field##, Val)
#define _INTC_EINT2_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_EINT2_ADDR, _INTC_EINT2_##Field##, AND, OR, INV)

#define _INTC_EINT2_RSVINT_SHIFT		(7)
#define _INTC_EINT2_RSVINT_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_RSVINT_SHIFT)
#define _INTC_EINT2_RSVINT_MASK			(_INTC_EINT2_RSVINT_MK(0x0001u))
#define _INTC_EINT2_RSVINT_CLR			(~(_INTC_EINT2_RSVINT_MASK))

#define _INTC_EINT2_CLKC_SHIFT		(6)
#define _INTC_EINT2_CLKC_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_CLKC_SHIFT)
#define _INTC_EINT2_CLKC_MASK			(_INTC_EINT2_CLKC_MK(0x0001u))
#define _INTC_EINT2_CLKC_CLR			(~(_INTC_EINT2_CLKC_MASK))

#define _INTC_EINT2_I2C_SHIFT		(5)
#define _INTC_EINT2_I2C_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_I2C_SHIFT)
#define _INTC_EINT2_I2C_MASK			(_INTC_EINT2_I2C_MK(0x0001u))
#define _INTC_EINT2_I2C_CLR			(~(_INTC_EINT2_I2C_MASK))

#define _INTC_EINT2_WDT_SHIFT		(4)
#define _INTC_EINT2_WDT_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_WDT_SHIFT)
#define _INTC_EINT2_WDT_MASK			(_INTC_EINT2_WDT_MK(0x0001u))
#define _INTC_EINT2_WDT_CLR			(~(_INTC_EINT2_WDT_MASK))

#define _INTC_EINT2_PREV_SHIFT		(3)
#define _INTC_EINT2_PREV_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_PREV_SHIFT)
#define _INTC_EINT2_PREV_MASK			(_INTC_EINT2_PREV_MK(0x0001u))
#define _INTC_EINT2_PREV_CLR			(~(_INTC_EINT2_PREV_MASK))

#define _INTC_EINT2_EXT15_SHIFT		(2)
#define _INTC_EINT2_EXT15_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_EXT15_SHIFT)
#define _INTC_EINT2_EXT15_MASK			(_INTC_EINT2_EXT15_MK(0x0001u))
#define _INTC_EINT2_EXT15_CLR			(~(_INTC_EINT2_EXT15_MASK))

#define _INTC_EINT2_EXT14_SHIFT		(1)
#define _INTC_EINT2_EXT14_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_EINT2_EXT14_SHIFT)
#define _INTC_EINT2_EXT14_MASK			(_INTC_EINT2_EXT14_MK(0x0001u))
#define _INTC_EINT2_EXT14_CLR			(~(_INTC_EINT2_EXT14_MASK))

#define _INTC_EINT2_EXT13_SHIFT		(0)
#define _INTC_EINT2_EXT13_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_EINT2_EXT13_MASK			(_INTC_EINT2_EXT13_MK(0x0001u))
#define _INTC_EINT2_EXT13_CLR			(~(_INTC_EINT2_EXT13_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC INTRAW register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_INTRAW_GET()			_REG_GET(_INTC_INTRAW_ADDR)
#define _INTC_INTRAW_SET(Val)			_REG_SET(_INTC_INTRAW_ADDR, Val)
#define _INTC_INTRAW_AOI(AND,OR,INV)		_REG_AOI(_INTC_INTRAW_ADDR,AND,OR,INV)
#define _INTC_INTRAW_FGET(Field)			_FIELD_GET(_INTC_INTRAW_ADDR, _INTC_INTRAW_##Field##)
#define _INTC_INTRAW_FSET(Field, Val)		_FIELD_SET(_INTC_INTRAW_ADDR, _INTC_INTRAW_##Field##, Val)
#define _INTC_INTRAW_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_INTRAW_ADDR, _INTC_INTRAW_##Field##, AND, OR, INV)

#define _INTC_INTRAW_IRQ_SHIFT		(1)
#define _INTC_INTRAW_IRQ_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_INTRAW_IRQ_SHIFT)
#define _INTC_INTRAW_IRQ_MASK			(_INTC_INTRAW_IRQ_MK(0x0001u))
#define _INTC_INTRAW_IRQ_CLR			(~(_INTC_INTRAW_IRQ_MASK))

#define _INTC_INTRAW_FIQ_SHIFT		(0)
#define _INTC_INTRAW_FIQ_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_INTRAW_FIQ_MASK			(_INTC_INTRAW_FIQ_MK(0x0001u))
#define _INTC_INTRAW_FIQ_CLR			(~(_INTC_INTRAW_FIQ_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC EABASE0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_EABASE0_GET()			_REG_GET(_INTC_EABASE0_ADDR)
#define _INTC_EABASE0_SET(Val)			_REG_SET(_INTC_EABASE0_ADDR, Val)
#define _INTC_EABASE0_AOI(AND,OR,INV)		_REG_AOI(_INTC_EABASE0_ADDR,AND,OR,INV)
#define _INTC_EABASE0_FGET(Field)			_FIELD_GET(_INTC_EABASE0_ADDR, _INTC_EABASE0_##Field##)
#define _INTC_EABASE0_FSET(Field, Val)		_FIELD_SET(_INTC_EABASE0_ADDR, _INTC_EABASE0_##Field##, Val)
#define _INTC_EABASE0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_EABASE0_ADDR, _INTC_EABASE0_##Field##, AND, OR, INV)

#define _INTC_EABASE0_EABL_SHIFT		(3)
#define _INTC_EABASE0_EABL_MK(n)		(((Uint16)(n) & 0x1fffu) << _INTC_EABASE0_EABL_SHIFT)
#define _INTC_EABASE0_EABL_MASK			(_INTC_EABASE0_EABL_MK(0x1fffu))
#define _INTC_EABASE0_EABL_CLR			(~(_INTC_EABASE0_EABL_MASK))

#define _INTC_EABASE0_TSIZE_SHIFT		(0)
#define _INTC_EABASE0_TSIZE_MK(n)		((Uint16)(n) & 0x0003u) 
#define _INTC_EABASE0_TSIZE_MASK			(_INTC_EABASE0_TSIZE_MK(0x0003u))
#define _INTC_EABASE0_TSIZE_CLR			(~(_INTC_EABASE0_TSIZE_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC EABASE1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_EABASE1_GET()			_REG_GET(_INTC_EABASE1_ADDR)
#define _INTC_EABASE1_SET(Val)			_REG_SET(_INTC_EABASE1_ADDR, Val)
#define _INTC_EABASE1_AOI(AND,OR,INV)		_REG_AOI(_INTC_EABASE1_ADDR,AND,OR,INV)
#define _INTC_EABASE1_FGET(Field)			_FIELD_GET(_INTC_EABASE1_ADDR, _INTC_EABASE1_##Field##)
#define _INTC_EABASE1_FSET(Field, Val)		_FIELD_SET(_INTC_EABASE1_ADDR, _INTC_EABASE1_##Field##, Val)
#define _INTC_EABASE1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_EABASE1_ADDR, _INTC_EABASE1_##Field##, AND, OR, INV)

#define _INTC_EABASE1_EABH_SHIFT		(0)
#define _INTC_EABASE1_EABH_MK(n)		((Uint16)(n) & 0x1fffu) 
#define _INTC_EABASE1_EABH_MASK			(_INTC_EABASE1_EABH_MK(0x1fffu))
#define _INTC_EABASE1_EABH_CLR			(~(_INTC_EABASE1_EABH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC INTPRI00 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_INTPRI00_GET()			_REG_GET(_INTC_INTPRI00_ADDR)
#define _INTC_INTPRI00_SET(Val)			_REG_SET(_INTC_INTPRI00_ADDR, Val)
#define _INTC_INTPRI00_AOI(AND,OR,INV)		_REG_AOI(_INTC_INTPRI00_ADDR,AND,OR,INV)
#define _INTC_INTPRI00_FGET(Field)			_FIELD_GET(_INTC_INTPRI00_ADDR, _INTC_INTPRI00_##Field##)
#define _INTC_INTPRI00_FSET(Field, Val)		_FIELD_SET(_INTC_INTPRI00_ADDR, _INTC_INTPRI00_##Field##, Val)
#define _INTC_INTPRI00_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_INTPRI00_ADDR, _INTC_INTPRI00_##Field##, AND, OR, INV)

#define _INTC_INTPRI00_PRI01_SHIFT		(8)
#define _INTC_INTPRI00_PRI01_MK(n)		(((Uint16)(n) & 0x003fu) << _INTC_INTPRI00_PRI01_SHIFT)
#define _INTC_INTPRI00_PRI01_MASK			(_INTC_INTPRI00_PRI01_MK(0x003fu))
#define _INTC_INTPRI00_PRI01_CLR			(~(_INTC_INTPRI00_PRI01_MASK))

#define _INTC_INTPRI00_PRI00_SHIFT		(0)
#define _INTC_INTPRI00_PRI00_MK(n)		((Uint16)(n) & 0x003fu) 
#define _INTC_INTPRI00_PRI00_MASK			(_INTC_INTPRI00_PRI00_MK(0x003fu))
#define _INTC_INTPRI00_PRI00_CLR			(~(_INTC_INTPRI00_PRI00_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC INTPRI01 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_INTPRI01_GET()			_REG_GET(_INTC_INTPRI01_ADDR)
#define _INTC_INTPRI01_SET(Val)			_REG_SET(_INTC_INTPRI01_ADDR, Val)
#define _INTC_INTPRI01_AOI(AND,OR,INV)		_REG_AOI(_INTC_INTPRI01_ADDR,AND,OR,INV)
#define _INTC_INTPRI01_FGET(Field)			_FIELD_GET(_INTC_INTPRI01_ADDR, _INTC_INTPRI01_##Field##)
#define _INTC_INTPRI01_FSET(Field, Val)		_FIELD_SET(_INTC_INTPRI01_ADDR, _INTC_INTPRI01_##Field##, Val)
#define _INTC_INTPRI01_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_INTPRI01_ADDR, _INTC_INTPRI01_##Field##, AND, OR, INV)

#define _INTC_INTPRI01_PRI03_SHIFT		(8)
#define _INTC_INTPRI01_PRI03_MK(n)		(((Uint16)(n) & 0x003fu) << _INTC_INTPRI01_PRI03_SHIFT)
#define _INTC_INTPRI01_PRI03_MASK			(_INTC_INTPRI01_PRI03_MK(0x003fu))
#define _INTC_INTPRI01_PRI03_CLR			(~(_INTC_INTPRI01_PRI03_MASK))

#define _INTC_INTPRI01_PRI02_SHIFT		(0)
#define _INTC_INTPRI01_PRI02_MK(n)		((Uint16)(n) & 0x003fu) 
#define _INTC_INTPRI01_PRI02_MASK			(_INTC_INTPRI01_PRI02_MK(0x003fu))
#define _INTC_INTPRI01_PRI02_CLR			(~(_INTC_INTPRI01_PRI02_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC INTPRI02 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_INTPRI02_GET()			_REG_GET(_INTC_INTPRI02_ADDR)
#define _INTC_INTPRI02_SET(Val)			_REG_SET(_INTC_INTPRI02_ADDR, Val)
#define _INTC_INTPRI02_AOI(AND,OR,INV)		_REG_AOI(_INTC_INTPRI02_ADDR,AND,OR,INV)
#define _INTC_INTPRI02_FGET(Field)			_FIELD_GET(_INTC_INTPRI02_ADDR, _INTC_INTPRI02_##Field##)
#define _INTC_INTPRI02_FSET(Field, Val)		_FIELD_SET(_INTC_INTPRI02_ADDR, _INTC_INTPRI02_##Field##, Val)
#define _INTC_INTPRI02_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_INTPRI02_ADDR, _INTC_INTPRI02_##Field##, AND, OR, INV)

#define _INTC_INTPRI02_PRI05_SHIFT		(8)
#define _INTC_INTPRI02_PRI05_MK(n)		(((Uint16)(n) & 0x003fu) << _INTC_INTPRI02_PRI05_SHIFT)
#define _INTC_INTPRI02_PRI05_MASK			(_INTC_INTPRI02_PRI05_MK(0x003fu))
#define _INTC_INTPRI02_PRI05_CLR			(~(_INTC_INTPRI02_PRI05_MASK))

#define _INTC_INTPRI02_PRI04_SHIFT		(0)
#define _INTC_INTPRI02_PRI04_MK(n)		((Uint16)(n) & 0x003fu) 
#define _INTC_INTPRI02_PRI04_MASK			(_INTC_INTPRI02_PRI04_MK(0x003fu))
#define _INTC_INTPRI02_PRI04_CLR			(~(_INTC_INTPRI02_PRI04_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC INTPRI03 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_INTPRI03_GET()			_REG_GET(_INTC_INTPRI03_ADDR)
#define _INTC_INTPRI03_SET(Val)			_REG_SET(_INTC_INTPRI03_ADDR, Val)
#define _INTC_INTPRI03_AOI(AND,OR,INV)		_REG_AOI(_INTC_INTPRI03_ADDR,AND,OR,INV)
#define _INTC_INTPRI03_FGET(Field)			_FIELD_GET(_INTC_INTPRI03_ADDR, _INTC_INTPRI03_##Field##)
#define _INTC_INTPRI03_FSET(Field, Val)		_FIELD_SET(_INTC_INTPRI03_ADDR, _INTC_INTPRI03_##Field##, Val)
#define _INTC_INTPRI03_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_INTPRI03_ADDR, _INTC_INTPRI03_##Field##, AND, OR, INV)

#define _INTC_INTPRI03_PRI07_SHIFT		(8)
#define _INTC_INTPRI03_PRI07_MK(n)		(((Uint16)(n) & 0x003fu) << _INTC_INTPRI03_PRI07_SHIFT)
#define _INTC_INTPRI03_PRI07_MASK			(_INTC_INTPRI03_PRI07_MK(0x003fu))
#define _INTC_INTPRI03_PRI07_CLR			(~(_INTC_INTPRI03_PRI07_MASK))

#define _INTC_INTPRI03_PRI06_SHIFT		(0)
#define _INTC_INTPRI03_PRI06_MK(n)		((Uint16)(n) & 0x003fu) 
#define _INTC_INTPRI03_PRI06_MASK			(_INTC_INTPRI03_PRI06_MK(0x003fu))
#define _INTC_INTPRI03_PRI06_CLR			(~