csl_intchal_270.h

dm270 source code

#define _INTC_IRQ2_PREV_MASK			(_INTC_IRQ2_PREV_MK(0x0001u))
#define _INTC_IRQ2_PREV_CLR			(~(_INTC_IRQ2_PREV_MASK))

#define _INTC_IRQ2_EXT15_SHIFT		(2)
#define _INTC_IRQ2_EXT15_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_IRQ2_EXT15_SHIFT)
#define _INTC_IRQ2_EXT15_MASK			(_INTC_IRQ2_EXT15_MK(0x0001u))
#define _INTC_IRQ2_EXT15_CLR			(~(_INTC_IRQ2_EXT15_MASK))

#define _INTC_IRQ2_EXT14_SHIFT		(1)
#define _INTC_IRQ2_EXT14_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_IRQ2_EXT14_SHIFT)
#define _INTC_IRQ2_EXT14_MASK			(_INTC_IRQ2_EXT14_MK(0x0001u))
#define _INTC_IRQ2_EXT14_CLR			(~(_INTC_IRQ2_EXT14_MASK))

#define _INTC_IRQ2_EXT13_SHIFT		(0)
#define _INTC_IRQ2_EXT13_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_IRQ2_EXT13_MASK			(_INTC_IRQ2_EXT13_MK(0x0001u))
#define _INTC_IRQ2_EXT13_CLR			(~(_INTC_IRQ2_EXT13_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC FIQENTRY0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FIQENTRY0_GET()			_REG_GET(_INTC_FIQENTRY0_ADDR)
#define _INTC_FIQENTRY0_SET(Val)			_REG_SET(_INTC_FIQENTRY0_ADDR, Val)
#define _INTC_FIQENTRY0_AOI(AND,OR,INV)		_REG_AOI(_INTC_FIQENTRY0_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for INTC FIQENTRY1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FIQENTRY1_GET()			_REG_GET(_INTC_FIQENTRY1_ADDR)
#define _INTC_FIQENTRY1_SET(Val)			_REG_SET(_INTC_FIQENTRY1_ADDR, Val)
#define _INTC_FIQENTRY1_AOI(AND,OR,INV)		_REG_AOI(_INTC_FIQENTRY1_ADDR,AND,OR,INV)
#define _INTC_FIQENTRY1_FGET(Field)			_FIELD_GET(_INTC_FIQENTRY1_ADDR, _INTC_FIQENTRY1_##Field##)
#define _INTC_FIQENTRY1_FSET(Field, Val)		_FIELD_SET(_INTC_FIQENTRY1_ADDR, _INTC_FIQENTRY1_##Field##, Val)
#define _INTC_FIQENTRY1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_FIQENTRY1_ADDR, _INTC_FIQENTRY1_##Field##, AND, OR, INV)

#define _INTC_FIQENTRY1_FIQE1_SHIFT		(0)
#define _INTC_FIQENTRY1_FIQE1_MK(n)		((Uint16)(n) & 0x1fffu) 
#define _INTC_FIQENTRY1_FIQE1_MASK			(_INTC_FIQENTRY1_FIQE1_MK(0x1fffu))
#define _INTC_FIQENTRY1_FIQE1_CLR			(~(_INTC_FIQENTRY1_FIQE1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC IRQENTRY0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_IRQENTRY0_GET()			_REG_GET(_INTC_IRQENTRY0_ADDR)
#define _INTC_IRQENTRY0_SET(Val)			_REG_SET(_INTC_IRQENTRY0_ADDR, Val)
#define _INTC_IRQENTRY0_AOI(AND,OR,INV)		_REG_AOI(_INTC_IRQENTRY0_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for INTC IRQENTRY1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_IRQENTRY1_GET()			_REG_GET(_INTC_IRQENTRY1_ADDR)
#define _INTC_IRQENTRY1_SET(Val)			_REG_SET(_INTC_IRQENTRY1_ADDR, Val)
#define _INTC_IRQENTRY1_AOI(AND,OR,INV)		_REG_AOI(_INTC_IRQENTRY1_ADDR,AND,OR,INV)
#define _INTC_IRQENTRY1_FGET(Field)			_FIELD_GET(_INTC_IRQENTRY1_ADDR, _INTC_IRQENTRY1_##Field##)
#define _INTC_IRQENTRY1_FSET(Field, Val)		_FIELD_SET(_INTC_IRQENTRY1_ADDR, _INTC_IRQENTRY1_##Field##, Val)
#define _INTC_IRQENTRY1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_IRQENTRY1_ADDR, _INTC_IRQENTRY1_##Field##, AND, OR, INV)

#define _INTC_IRQENTRY1_IRQE1_SHIFT		(0)
#define _INTC_IRQENTRY1_IRQE1_MK(n)		((Uint16)(n) & 0x1fffu) 
#define _INTC_IRQENTRY1_IRQE1_MASK			(_INTC_IRQENTRY1_IRQE1_MK(0x1fffu))
#define _INTC_IRQENTRY1_IRQE1_CLR			(~(_INTC_IRQENTRY1_IRQE1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC FISEL0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FISEL0_GET()			_REG_GET(_INTC_FISEL0_ADDR)
#define _INTC_FISEL0_SET(Val)			_REG_SET(_INTC_FISEL0_ADDR, Val)
#define _INTC_FISEL0_AOI(AND,OR,INV)		_REG_AOI(_INTC_FISEL0_ADDR,AND,OR,INV)
#define _INTC_FISEL0_FGET(Field)			_FIELD_GET(_INTC_FISEL0_ADDR, _INTC_FISEL0_##Field##)
#define _INTC_FISEL0_FSET(Field, Val)		_FIELD_SET(_INTC_FISEL0_ADDR, _INTC_FISEL0_##Field##, Val)
#define _INTC_FISEL0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_FISEL0_ADDR, _INTC_FISEL0_##Field##, AND, OR, INV)

#define _INTC_FISEL0_MTC0_SHIFT		(15)
#define _INTC_FISEL0_MTC0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_MTC0_SHIFT)
#define _INTC_FISEL0_MTC0_MASK			(_INTC_FISEL0_MTC0_MK(0x0001u))
#define _INTC_FISEL0_MTC0_CLR			(~(_INTC_FISEL0_MTC0_MASK))

#define _INTC_FISEL0_USB_SHIFT		(14)
#define _INTC_FISEL0_USB_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_USB_SHIFT)
#define _INTC_FISEL0_USB_MASK			(_INTC_FISEL0_USB_MK(0x0001u))
#define _INTC_FISEL0_USB_CLR			(~(_INTC_FISEL0_USB_MASK))

#define _INTC_FISEL0_UART1_SHIFT		(13)
#define _INTC_FISEL0_UART1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_UART1_SHIFT)
#define _INTC_FISEL0_UART1_MASK			(_INTC_FISEL0_UART1_MK(0x0001u))
#define _INTC_FISEL0_UART1_CLR			(~(_INTC_FISEL0_UART1_MASK))

#define _INTC_FISEL0_UART0_SHIFT		(12)
#define _INTC_FISEL0_UART0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_UART0_SHIFT)
#define _INTC_FISEL0_UART0_MASK			(_INTC_FISEL0_UART0_MK(0x0001u))
#define _INTC_FISEL0_UART0_CLR			(~(_INTC_FISEL0_UART0_MASK))

#define _INTC_FISEL0_DSPHINT_SHIFT		(11)
#define _INTC_FISEL0_DSPHINT_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_DSPHINT_SHIFT)
#define _INTC_FISEL0_DSPHINT_MASK			(_INTC_FISEL0_DSPHINT_MK(0x0001u))
#define _INTC_FISEL0_DSPHINT_CLR			(~(_INTC_FISEL0_DSPHINT_MASK))

#define _INTC_FISEL0_EXTHOST_SHIFT		(10)
#define _INTC_FISEL0_EXTHOST_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_EXTHOST_SHIFT)
#define _INTC_FISEL0_EXTHOST_MASK			(_INTC_FISEL0_EXTHOST_MK(0x0001u))
#define _INTC_FISEL0_EXTHOST_CLR			(~(_INTC_FISEL0_EXTHOST_MASK))

#define _INTC_FISEL0_SP1_SHIFT		(9)
#define _INTC_FISEL0_SP1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_SP1_SHIFT)
#define _INTC_FISEL0_SP1_MASK			(_INTC_FISEL0_SP1_MK(0x0001u))
#define _INTC_FISEL0_SP1_CLR			(~(_INTC_FISEL0_SP1_MASK))

#define _INTC_FISEL0_SP0_SHIFT		(8)
#define _INTC_FISEL0_SP0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_SP0_SHIFT)
#define _INTC_FISEL0_SP0_MASK			(_INTC_FISEL0_SP0_MK(0x0001u))
#define _INTC_FISEL0_SP0_CLR			(~(_INTC_FISEL0_SP0_MASK))

#define _INTC_FISEL0_OSD_SHIFT		(7)
#define _INTC_FISEL0_OSD_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_OSD_SHIFT)
#define _INTC_FISEL0_OSD_MASK			(_INTC_FISEL0_OSD_MK(0x0001u))
#define _INTC_FISEL0_OSD_CLR			(~(_INTC_FISEL0_OSD_MASK))

#define _INTC_FISEL0_CCDVD2_SHIFT		(6)
#define _INTC_FISEL0_CCDVD2_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_CCDVD2_SHIFT)
#define _INTC_FISEL0_CCDVD2_MASK			(_INTC_FISEL0_CCDVD2_MK(0x0001u))
#define _INTC_FISEL0_CCDVD2_CLR			(~(_INTC_FISEL0_CCDVD2_MASK))

#define _INTC_FISEL0_CCDVD1_SHIFT		(5)
#define _INTC_FISEL0_CCDVD1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_CCDVD1_SHIFT)
#define _INTC_FISEL0_CCDVD1_MASK			(_INTC_FISEL0_CCDVD1_MK(0x0001u))
#define _INTC_FISEL0_CCDVD1_CLR			(~(_INTC_FISEL0_CCDVD1_MASK))

#define _INTC_FISEL0_CCDVD0_SHIFT		(4)
#define _INTC_FISEL0_CCDVD0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_CCDVD0_SHIFT)
#define _INTC_FISEL0_CCDVD0_MASK			(_INTC_FISEL0_CCDVD0_MK(0x0001u))
#define _INTC_FISEL0_CCDVD0_CLR			(~(_INTC_FISEL0_CCDVD0_MASK))

#define _INTC_FISEL0_TMR3_SHIFT		(3)
#define _INTC_FISEL0_TMR3_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_TMR3_SHIFT)
#define _INTC_FISEL0_TMR3_MASK			(_INTC_FISEL0_TMR3_MK(0x0001u))
#define _INTC_FISEL0_TMR3_CLR			(~(_INTC_FISEL0_TMR3_MASK))

#define _INTC_FISEL0_TMR2_SHIFT		(2)
#define _INTC_FISEL0_TMR2_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_TMR2_SHIFT)
#define _INTC_FISEL0_TMR2_MASK			(_INTC_FISEL0_TMR2_MK(0x0001u))
#define _INTC_FISEL0_TMR2_CLR			(~(_INTC_FISEL0_TMR2_MASK))

#define _INTC_FISEL0_TMR1_SHIFT		(1)
#define _INTC_FISEL0_TMR1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL0_TMR1_SHIFT)
#define _INTC_FISEL0_TMR1_MASK			(_INTC_FISEL0_TMR1_MK(0x0001u))
#define _INTC_FISEL0_TMR1_CLR			(~(_INTC_FISEL0_TMR1_MASK))

#define _INTC_FISEL0_TMR0_SHIFT		(0)
#define _INTC_FISEL0_TMR0_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_FISEL0_TMR0_MASK			(_INTC_FISEL0_TMR0_MK(0x0001u))
#define _INTC_FISEL0_TMR0_CLR			(~(_INTC_FISEL0_TMR0_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC FISEL1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FISEL1_GET()			_REG_GET(_INTC_FISEL1_ADDR)
#define _INTC_FISEL1_SET(Val)			_REG_SET(_INTC_FISEL1_ADDR, Val)
#define _INTC_FISEL1_AOI(AND,OR,INV)		_REG_AOI(_INTC_FISEL1_ADDR,AND,OR,INV)
#define _INTC_FISEL1_FGET(Field)			_FIELD_GET(_INTC_FISEL1_ADDR, _INTC_FISEL1_##Field##)
#define _INTC_FISEL1_FSET(Field, Val)		_FIELD_SET(_INTC_FISEL1_ADDR, _INTC_FISEL1_##Field##, Val)
#define _INTC_FISEL1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_FISEL1_ADDR, _INTC_FISEL1_##Field##, AND, OR, INV)

#define _INTC_FISEL1_EXT12_SHIFT		(15)
#define _INTC_FISEL1_EXT12_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT12_SHIFT)
#define _INTC_FISEL1_EXT12_MASK			(_INTC_FISEL1_EXT12_MK(0x0001u))
#define _INTC_FISEL1_EXT12_CLR			(~(_INTC_FISEL1_EXT12_MASK))

#define _INTC_FISEL1_EXT11_SHIFT		(14)
#define _INTC_FISEL1_EXT11_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT11_SHIFT)
#define _INTC_FISEL1_EXT11_MASK			(_INTC_FISEL1_EXT11_MK(0x0001u))
#define _INTC_FISEL1_EXT11_CLR			(~(_INTC_FISEL1_EXT11_MASK))

#define _INTC_FISEL1_EXT10_SHIFT		(13)
#define _INTC_FISEL1_EXT10_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT10_SHIFT)
#define _INTC_FISEL1_EXT10_MASK			(_INTC_FISEL1_EXT10_MK(0x0001u))
#define _INTC_FISEL1_EXT10_CLR			(~(_INTC_FISEL1_EXT10_MASK))

#define _INTC_FISEL1_EXT9_SHIFT		(12)
#define _INTC_FISEL1_EXT9_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT9_SHIFT)
#define _INTC_FISEL1_EXT9_MASK			(_INTC_FISEL1_EXT9_MK(0x0001u))
#define _INTC_FISEL1_EXT9_CLR			(~(_INTC_FISEL1_EXT9_MASK))

#define _INTC_FISEL1_EXT8_SHIFT		(11)
#define _INTC_FISEL1_EXT8_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT8_SHIFT)
#define _INTC_FISEL1_EXT8_MASK			(_INTC_FISEL1_EXT8_MK(0x0001u))
#define _INTC_FISEL1_EXT8_CLR			(~(_INTC_FISEL1_EXT8_MASK))

#define _INTC_FISEL1_EXT7_SHIFT		(10)
#define _INTC_FISEL1_EXT7_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT7_SHIFT)
#define _INTC_FISEL1_EXT7_MASK			(_INTC_FISEL1_EXT7_MK(0x0001u))
#define _INTC_FISEL1_EXT7_CLR			(~(_INTC_FISEL1_EXT7_MASK))

#define _INTC_FISEL1_EXT6_SHIFT		(9)
#define _INTC_FISEL1_EXT6_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT6_SHIFT)
#define _INTC_FISEL1_EXT6_MASK			(_INTC_FISEL1_EXT6_MK(0x0001u))
#define _INTC_FISEL1_EXT6_CLR			(~(_INTC_FISEL1_EXT6_MASK))

#define _INTC_FISEL1_EXT5_SHIFT		(8)
#define _INTC_FISEL1_EXT5_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT5_SHIFT)
#define _INTC_FISEL1_EXT5_MASK			(_INTC_FISEL1_EXT5_MK(0x0001u))
#define _INTC_FISEL1_EXT5_CLR			(~(_INTC_FISEL1_EXT5_MASK))

#define _INTC_FISEL1_EXT4_SHIFT		(7)
#define _INTC_FISEL1_EXT4_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT4_SHIFT)
#define _INTC_FISEL1_EXT4_MASK			(_INTC_FISEL1_EXT4_MK(0x0001u))
#define _INTC_FISEL1_EXT4_CLR			(~(_INTC_FISEL1_EXT4_MASK))

#define _INTC_FISEL1_EXT3_SHIFT		(6)
#define _INTC_FISEL1_EXT3_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT3_SHIFT)
#define _INTC_FISEL1_EXT3_MASK			(_INTC_FISEL1_EXT3_MK(0x0001u))
#define _INTC_FISEL1_EXT3_CLR			(~(_INTC_FISEL1_EXT3_MASK))

#define _INTC_FISEL1_EXT2_SHIFT		(5)
#define _INTC_FISEL1_EXT2_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FISEL1_EXT2_SHIFT)
#define _INTC_FISEL1_EXT2_MASK			(_INTC_FISEL1_EXT2_MK(0x0001u))
#define _INTC_FISEL1_EXT2_CLR			(~(_INTC_FISEL1_EXT2_MASK))

#define _INTC_FISEL1_EXT1_SHIFT		(4)