csl_intchal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... INTC - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_intchal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for INTC:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for INTC FIQ0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FIQ0_GET()			_REG_GET(_INTC_FIQ0_ADDR)
#define _INTC_FIQ0_SET(Val)			_REG_SET(_INTC_FIQ0_ADDR, Val)
#define _INTC_FIQ0_AOI(AND,OR,INV)		_REG_AOI(_INTC_FIQ0_ADDR,AND,OR,INV)
#define _INTC_FIQ0_FGET(Field)			_FIELD_GET(_INTC_FIQ0_ADDR, _INTC_FIQ0_##Field##)
#define _INTC_FIQ0_FSET(Field, Val)		_FIELD_SET(_INTC_FIQ0_ADDR, _INTC_FIQ0_##Field##, Val)
#define _INTC_FIQ0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_FIQ0_ADDR, _INTC_FIQ0_##Field##, AND, OR, INV)

#define _INTC_FIQ0_MTC0_SHIFT		(15)
#define _INTC_FIQ0_MTC0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_MTC0_SHIFT)
#define _INTC_FIQ0_MTC0_MASK			(_INTC_FIQ0_MTC0_MK(0x0001u))
#define _INTC_FIQ0_MTC0_CLR			(~(_INTC_FIQ0_MTC0_MASK))

#define _INTC_FIQ0_USB_SHIFT		(14)
#define _INTC_FIQ0_USB_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_USB_SHIFT)
#define _INTC_FIQ0_USB_MASK			(_INTC_FIQ0_USB_MK(0x0001u))
#define _INTC_FIQ0_USB_CLR			(~(_INTC_FIQ0_USB_MASK))

#define _INTC_FIQ0_UART1_SHIFT		(13)
#define _INTC_FIQ0_UART1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_UART1_SHIFT)
#define _INTC_FIQ0_UART1_MASK			(_INTC_FIQ0_UART1_MK(0x0001u))
#define _INTC_FIQ0_UART1_CLR			(~(_INTC_FIQ0_UART1_MASK))

#define _INTC_FIQ0_UART0_SHIFT		(12)
#define _INTC_FIQ0_UART0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_UART0_SHIFT)
#define _INTC_FIQ0_UART0_MASK			(_INTC_FIQ0_UART0_MK(0x0001u))
#define _INTC_FIQ0_UART0_CLR			(~(_INTC_FIQ0_UART0_MASK))

#define _INTC_FIQ0_DSPHINT_SHIFT		(11)
#define _INTC_FIQ0_DSPHINT_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_DSPHINT_SHIFT)
#define _INTC_FIQ0_DSPHINT_MASK			(_INTC_FIQ0_DSPHINT_MK(0x0001u))
#define _INTC_FIQ0_DSPHINT_CLR			(~(_INTC_FIQ0_DSPHINT_MASK))

#define _INTC_FIQ0_EXTHOST_SHIFT		(10)
#define _INTC_FIQ0_EXTHOST_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_EXTHOST_SHIFT)
#define _INTC_FIQ0_EXTHOST_MASK			(_INTC_FIQ0_EXTHOST_MK(0x0001u))
#define _INTC_FIQ0_EXTHOST_CLR			(~(_INTC_FIQ0_EXTHOST_MASK))

#define _INTC_FIQ0_SP1_SHIFT		(9)
#define _INTC_FIQ0_SP1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_SP1_SHIFT)
#define _INTC_FIQ0_SP1_MASK			(_INTC_FIQ0_SP1_MK(0x0001u))
#define _INTC_FIQ0_SP1_CLR			(~(_INTC_FIQ0_SP1_MASK))

#define _INTC_FIQ0_SP0_SHIFT		(8)
#define _INTC_FIQ0_SP0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_SP0_SHIFT)
#define _INTC_FIQ0_SP0_MASK			(_INTC_FIQ0_SP0_MK(0x0001u))
#define _INTC_FIQ0_SP0_CLR			(~(_INTC_FIQ0_SP0_MASK))

#define _INTC_FIQ0_OSD_SHIFT		(7)
#define _INTC_FIQ0_OSD_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_OSD_SHIFT)
#define _INTC_FIQ0_OSD_MASK			(_INTC_FIQ0_OSD_MK(0x0001u))
#define _INTC_FIQ0_OSD_CLR			(~(_INTC_FIQ0_OSD_MASK))

#define _INTC_FIQ0_CCDVD2_SHIFT		(6)
#define _INTC_FIQ0_CCDVD2_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_CCDVD2_SHIFT)
#define _INTC_FIQ0_CCDVD2_MASK			(_INTC_FIQ0_CCDVD2_MK(0x0001u))
#define _INTC_FIQ0_CCDVD2_CLR			(~(_INTC_FIQ0_CCDVD2_MASK))

#define _INTC_FIQ0_CCDVD1_SHIFT		(5)
#define _INTC_FIQ0_CCDVD1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_CCDVD1_SHIFT)
#define _INTC_FIQ0_CCDVD1_MASK			(_INTC_FIQ0_CCDVD1_MK(0x0001u))
#define _INTC_FIQ0_CCDVD1_CLR			(~(_INTC_FIQ0_CCDVD1_MASK))

#define _INTC_FIQ0_CCDVD0_SHIFT		(4)
#define _INTC_FIQ0_CCDVD0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_CCDVD0_SHIFT)
#define _INTC_FIQ0_CCDVD0_MASK			(_INTC_FIQ0_CCDVD0_MK(0x0001u))
#define _INTC_FIQ0_CCDVD0_CLR			(~(_INTC_FIQ0_CCDVD0_MASK))

#define _INTC_FIQ0_TMR3_SHIFT		(3)
#define _INTC_FIQ0_TMR3_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_TMR3_SHIFT)
#define _INTC_FIQ0_TMR3_MASK			(_INTC_FIQ0_TMR3_MK(0x0001u))
#define _INTC_FIQ0_TMR3_CLR			(~(_INTC_FIQ0_TMR3_MASK))

#define _INTC_FIQ0_TMR2_SHIFT		(2)
#define _INTC_FIQ0_TMR2_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_TMR2_SHIFT)
#define _INTC_FIQ0_TMR2_MASK			(_INTC_FIQ0_TMR2_MK(0x0001u))
#define _INTC_FIQ0_TMR2_CLR			(~(_INTC_FIQ0_TMR2_MASK))

#define _INTC_FIQ0_TMR1_SHIFT		(1)
#define _INTC_FIQ0_TMR1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ0_TMR1_SHIFT)
#define _INTC_FIQ0_TMR1_MASK			(_INTC_FIQ0_TMR1_MK(0x0001u))
#define _INTC_FIQ0_TMR1_CLR			(~(_INTC_FIQ0_TMR1_MASK))

#define _INTC_FIQ0_TMR0_SHIFT		(0)
#define _INTC_FIQ0_TMR0_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_FIQ0_TMR0_MASK			(_INTC_FIQ0_TMR0_MK(0x0001u))
#define _INTC_FIQ0_TMR0_CLR			(~(_INTC_FIQ0_TMR0_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC FIQ1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FIQ1_GET()			_REG_GET(_INTC_FIQ1_ADDR)
#define _INTC_FIQ1_SET(Val)			_REG_SET(_INTC_FIQ1_ADDR, Val)
#define _INTC_FIQ1_AOI(AND,OR,INV)		_REG_AOI(_INTC_FIQ1_ADDR,AND,OR,INV)
#define _INTC_FIQ1_FGET(Field)			_FIELD_GET(_INTC_FIQ1_ADDR, _INTC_FIQ1_##Field##)
#define _INTC_FIQ1_FSET(Field, Val)		_FIELD_SET(_INTC_FIQ1_ADDR, _INTC_FIQ1_##Field##, Val)
#define _INTC_FIQ1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_FIQ1_ADDR, _INTC_FIQ1_##Field##, AND, OR, INV)

#define _INTC_FIQ1_EXT12_SHIFT		(15)
#define _INTC_FIQ1_EXT12_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT12_SHIFT)
#define _INTC_FIQ1_EXT12_MASK			(_INTC_FIQ1_EXT12_MK(0x0001u))
#define _INTC_FIQ1_EXT12_CLR			(~(_INTC_FIQ1_EXT12_MASK))

#define _INTC_FIQ1_EXT11_SHIFT		(14)
#define _INTC_FIQ1_EXT11_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT11_SHIFT)
#define _INTC_FIQ1_EXT11_MASK			(_INTC_FIQ1_EXT11_MK(0x0001u))
#define _INTC_FIQ1_EXT11_CLR			(~(_INTC_FIQ1_EXT11_MASK))

#define _INTC_FIQ1_EXT10_SHIFT		(13)
#define _INTC_FIQ1_EXT10_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT10_SHIFT)
#define _INTC_FIQ1_EXT10_MASK			(_INTC_FIQ1_EXT10_MK(0x0001u))
#define _INTC_FIQ1_EXT10_CLR			(~(_INTC_FIQ1_EXT10_MASK))

#define _INTC_FIQ1_EXT9_SHIFT		(12)
#define _INTC_FIQ1_EXT9_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT9_SHIFT)
#define _INTC_FIQ1_EXT9_MASK			(_INTC_FIQ1_EXT9_MK(0x0001u))
#define _INTC_FIQ1_EXT9_CLR			(~(_INTC_FIQ1_EXT9_MASK))

#define _INTC_FIQ1_EXT8_SHIFT		(11)
#define _INTC_FIQ1_EXT8_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT8_SHIFT)
#define _INTC_FIQ1_EXT8_MASK			(_INTC_FIQ1_EXT8_MK(0x0001u))
#define _INTC_FIQ1_EXT8_CLR			(~(_INTC_FIQ1_EXT8_MASK))

#define _INTC_FIQ1_EXT7_SHIFT		(10)
#define _INTC_FIQ1_EXT7_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT7_SHIFT)
#define _INTC_FIQ1_EXT7_MASK			(_INTC_FIQ1_EXT7_MK(0x0001u))
#define _INTC_FIQ1_EXT7_CLR			(~(_INTC_FIQ1_EXT7_MASK))

#define _INTC_FIQ1_EXT6_SHIFT		(9)
#define _INTC_FIQ1_EXT6_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT6_SHIFT)
#define _INTC_FIQ1_EXT6_MASK			(_INTC_FIQ1_EXT6_MK(0x0001u))
#define _INTC_FIQ1_EXT6_CLR			(~(_INTC_FIQ1_EXT6_MASK))

#define _INTC_FIQ1_EXT5_SHIFT		(8)
#define _INTC_FIQ1_EXT5_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT5_SHIFT)
#define _INTC_FIQ1_EXT5_MASK			(_INTC_FIQ1_EXT5_MK(0x0001u))
#define _INTC_FIQ1_EXT5_CLR			(~(_INTC_FIQ1_EXT5_MASK))

#define _INTC_FIQ1_EXT4_SHIFT		(7)
#define _INTC_FIQ1_EXT4_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT4_SHIFT)
#define _INTC_FIQ1_EXT4_MASK			(_INTC_FIQ1_EXT4_MK(0x0001u))
#define _INTC_FIQ1_EXT4_CLR			(~(_INTC_FIQ1_EXT4_MASK))

#define _INTC_FIQ1_EXT3_SHIFT		(6)
#define _INTC_FIQ1_EXT3_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT3_SHIFT)
#define _INTC_FIQ1_EXT3_MASK			(_INTC_FIQ1_EXT3_MK(0x0001u))
#define _INTC_FIQ1_EXT3_CLR			(~(_INTC_FIQ1_EXT3_MASK))

#define _INTC_FIQ1_EXT2_SHIFT		(5)
#define _INTC_FIQ1_EXT2_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT2_SHIFT)
#define _INTC_FIQ1_EXT2_MASK			(_INTC_FIQ1_EXT2_MK(0x0001u))
#define _INTC_FIQ1_EXT2_CLR			(~(_INTC_FIQ1_EXT2_MASK))

#define _INTC_FIQ1_EXT1_SHIFT		(4)
#define _INTC_FIQ1_EXT1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT1_SHIFT)
#define _INTC_FIQ1_EXT1_MASK			(_INTC_FIQ1_EXT1_MK(0x0001u))
#define _INTC_FIQ1_EXT1_CLR			(~(_INTC_FIQ1_EXT1_MASK))

#define _INTC_FIQ1_EXT0_SHIFT		(3)
#define _INTC_FIQ1_EXT0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_EXT0_SHIFT)
#define _INTC_FIQ1_EXT0_MASK			(_INTC_FIQ1_EXT0_MK(0x0001u))
#define _INTC_FIQ1_EXT0_CLR			(~(_INTC_FIQ1_EXT0_MASK))

#define _INTC_FIQ1_MMCSD1_SHIFT		(2)
#define _INTC_FIQ1_MMCSD1_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_MMCSD1_SHIFT)
#define _INTC_FIQ1_MMCSD1_MASK			(_INTC_FIQ1_MMCSD1_MK(0x0001u))
#define _INTC_FIQ1_MMCSD1_CLR			(~(_INTC_FIQ1_MMCSD1_MASK))

#define _INTC_FIQ1_MMCSD0_SHIFT		(1)
#define _INTC_FIQ1_MMCSD0_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ1_MMCSD0_SHIFT)
#define _INTC_FIQ1_MMCSD0_MASK			(_INTC_FIQ1_MMCSD0_MK(0x0001u))
#define _INTC_FIQ1_MMCSD0_CLR			(~(_INTC_FIQ1_MMCSD0_MASK))

#define _INTC_FIQ1_MTC1_SHIFT		(0)
#define _INTC_FIQ1_MTC1_MK(n)		((Uint16)(n) & 0x0001u) 
#define _INTC_FIQ1_MTC1_MASK			(_INTC_FIQ1_MTC1_MK(0x0001u))
#define _INTC_FIQ1_MTC1_CLR			(~(_INTC_FIQ1_MTC1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for INTC FIQ2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _INTC_FIQ2_GET()			_REG_GET(_INTC_FIQ2_ADDR)
#define _INTC_FIQ2_SET(Val)			_REG_SET(_INTC_FIQ2_ADDR, Val)
#define _INTC_FIQ2_AOI(AND,OR,INV)		_REG_AOI(_INTC_FIQ2_ADDR,AND,OR,INV)
#define _INTC_FIQ2_FGET(Field)			_FIELD_GET(_INTC_FIQ2_ADDR, _INTC_FIQ2_##Field##)
#define _INTC_FIQ2_FSET(Field, Val)		_FIELD_SET(_INTC_FIQ2_ADDR, _INTC_FIQ2_##Field##, Val)
#define _INTC_FIQ2_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_INTC_FIQ2_ADDR, _INTC_FIQ2_##Field##, AND, OR, INV)

#define _INTC_FIQ2_RSVINT_SHIFT		(7)
#define _INTC_FIQ2_RSVINT_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ2_RSVINT_SHIFT)
#define _INTC_FIQ2_RSVINT_MASK			(_INTC_FIQ2_RSVINT_MK(0x0001u))
#define _INTC_FIQ2_RSVINT_CLR			(~(_INTC_FIQ2_RSVINT_MASK))

#define _INTC_FIQ2_CLKC_SHIFT		(6)
#define _INTC_FIQ2_CLKC_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ2_CLKC_SHIFT)
#define _INTC_FIQ2_CLKC_MASK			(_INTC_FIQ2_CLKC_MK(0x0001u))
#define _INTC_FIQ2_CLKC_CLR			(~(_INTC_FIQ2_CLKC_MASK))

#define _INTC_FIQ2_I2C_SHIFT		(5)
#define _INTC_FIQ2_I2C_MK(n)		(((Uint16)(n) & 0x0001u) << _INTC_FIQ2_I2C_SHIFT)
#define _INTC_FIQ2_I2C_MASK			(_INTC_FIQ2_I2C_MK(0x0001u))
#define _INTC_FIQ2_I2C_CLR			(~(_INTC_FIQ2_I2C_MASK))

#define _INTC_FIQ2_WDT_SHIFT		(4)