csl_sp0hal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... SP0 - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_sp0hal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for SP0:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for SP0 TXDATA0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_TXDATA0_GET()			_REG_GET(_SP0_TXDATA0_ADDR)
#define _SP0_TXDATA0_SET(Val)			_REG_SET(_SP0_TXDATA0_ADDR, Val)
#define _SP0_TXDATA0_AOI(AND,OR,INV)		_REG_AOI(_SP0_TXDATA0_ADDR,AND,OR,INV)
#define _SP0_TXDATA0_FGET(Field)			_FIELD_GET(_SP0_TXDATA0_ADDR, _SP0_TXDATA0_##Field##)
#define _SP0_TXDATA0_FSET(Field, Val)		_FIELD_SET(_SP0_TXDATA0_ADDR, _SP0_TXDATA0_##Field##, Val)
#define _SP0_TXDATA0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_TXDATA0_ADDR, _SP0_TXDATA0_##Field##, AND, OR, INV)

#define _SP0_TXDATA0_TXD_SHIFT		(0)
#define _SP0_TXDATA0_TXD_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _SP0_TXDATA0_TXD_MASK			(_SP0_TXDATA0_TXD_MK(0x00ffu))
#define _SP0_TXDATA0_TXD_CLR			(~(_SP0_TXDATA0_TXD_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 RXDATA0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_RXDATA0_GET()			_REG_GET(_SP0_RXDATA0_ADDR)
#define _SP0_RXDATA0_SET(Val)			_REG_SET(_SP0_RXDATA0_ADDR, Val)
#define _SP0_RXDATA0_AOI(AND,OR,INV)		_REG_AOI(_SP0_RXDATA0_ADDR,AND,OR,INV)
#define _SP0_RXDATA0_FGET(Field)			_FIELD_GET(_SP0_RXDATA0_ADDR, _SP0_RXDATA0_##Field##)
#define _SP0_RXDATA0_FSET(Field, Val)		_FIELD_SET(_SP0_RXDATA0_ADDR, _SP0_RXDATA0_##Field##, Val)
#define _SP0_RXDATA0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_RXDATA0_ADDR, _SP0_RXDATA0_##Field##, AND, OR, INV)

#define _SP0_RXDATA0_XMIT_SHIFT		(8)
#define _SP0_RXDATA0_XMIT_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_RXDATA0_XMIT_SHIFT)
#define _SP0_RXDATA0_XMIT_MASK			(_SP0_RXDATA0_XMIT_MK(0x0001u))
#define _SP0_RXDATA0_XMIT_CLR			(~(_SP0_RXDATA0_XMIT_MASK))

#define _SP0_RXDATA0_RXD_SHIFT		(0)
#define _SP0_RXDATA0_RXD_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _SP0_RXDATA0_RXD_MASK			(_SP0_RXDATA0_RXD_MK(0x00ffu))
#define _SP0_RXDATA0_RXD_CLR			(~(_SP0_RXDATA0_RXD_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 SIOEN0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_SIOEN0_GET()			_REG_GET(_SP0_SIOEN0_ADDR)
#define _SP0_SIOEN0_SET(Val)			_REG_SET(_SP0_SIOEN0_ADDR, Val)
#define _SP0_SIOEN0_AOI(AND,OR,INV)		_REG_AOI(_SP0_SIOEN0_ADDR,AND,OR,INV)
#define _SP0_SIOEN0_FGET(Field)			_FIELD_GET(_SP0_SIOEN0_ADDR, _SP0_SIOEN0_##Field##)
#define _SP0_SIOEN0_FSET(Field, Val)		_FIELD_SET(_SP0_SIOEN0_ADDR, _SP0_SIOEN0_##Field##, Val)
#define _SP0_SIOEN0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_SIOEN0_ADDR, _SP0_SIOEN0_##Field##, AND, OR, INV)

#define _SP0_SIOEN0_SIOEN_SHIFT		(0)
#define _SP0_SIOEN0_SIOEN_MK(n)		((Uint16)(n) & 0x0001u) 
#define _SP0_SIOEN0_SIOEN_MASK			(_SP0_SIOEN0_SIOEN_MK(0x0001u))
#define _SP0_SIOEN0_SIOEN_CLR			(~(_SP0_SIOEN0_SIOEN_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 SIOMODE0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_SIOMODE0_GET()			_REG_GET(_SP0_SIOMODE0_ADDR)
#define _SP0_SIOMODE0_SET(Val)			_REG_SET(_SP0_SIOMODE0_ADDR, Val)
#define _SP0_SIOMODE0_AOI(AND,OR,INV)		_REG_AOI(_SP0_SIOMODE0_ADDR,AND,OR,INV)
#define _SP0_SIOMODE0_FGET(Field)			_FIELD_GET(_SP0_SIOMODE0_ADDR, _SP0_SIOMODE0_##Field##)
#define _SP0_SIOMODE0_FSET(Field, Val)		_FIELD_SET(_SP0_SIOMODE0_ADDR, _SP0_SIOMODE0_##Field##, Val)
#define _SP0_SIOMODE0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_SIOMODE0_ADDR, _SP0_SIOMODE0_##Field##, AND, OR, INV)

#define _SP0_SIOMODE0_SLVEN_SHIFT		(12)
#define _SP0_SIOMODE0_SLVEN_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_SIOMODE0_SLVEN_SHIFT)
#define _SP0_SIOMODE0_SLVEN_MASK			(_SP0_SIOMODE0_SLVEN_MK(0x0001u))
#define _SP0_SIOMODE0_SLVEN_CLR			(~(_SP0_SIOMODE0_SLVEN_MASK))

#define _SP0_SIOMODE0_SIOCLR_SHIFT		(11)
#define _SP0_SIOMODE0_SIOCLR_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_SIOMODE0_SIOCLR_SHIFT)
#define _SP0_SIOMODE0_SIOCLR_MASK			(_SP0_SIOMODE0_SIOCLR_MK(0x0001u))
#define _SP0_SIOMODE0_SIOCLR_CLR			(~(_SP0_SIOMODE0_SIOCLR_MASK))

#define _SP0_SIOMODE0_SCLKM_SHIFT		(10)
#define _SP0_SIOMODE0_SCLKM_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_SIOMODE0_SCLKM_SHIFT)
#define _SP0_SIOMODE0_SCLKM_MASK			(_SP0_SIOMODE0_SCLKM_MK(0x0001u))
#define _SP0_SIOMODE0_SCLKM_CLR			(~(_SP0_SIOMODE0_SCLKM_MASK))

#define _SP0_SIOMODE0_MSB_SHIFT		(9)
#define _SP0_SIOMODE0_MSB_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_SIOMODE0_MSB_SHIFT)
#define _SP0_SIOMODE0_MSB_MASK			(_SP0_SIOMODE0_MSB_MK(0x0001u))
#define _SP0_SIOMODE0_MSB_CLR			(~(_SP0_SIOMODE0_MSB_MASK))

#define _SP0_SIOMODE0_MSSEL_SHIFT		(8)
#define _SP0_SIOMODE0_MSSEL_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_SIOMODE0_MSSEL_SHIFT)
#define _SP0_SIOMODE0_MSSEL_MASK			(_SP0_SIOMODE0_MSSEL_MK(0x0001u))
#define _SP0_SIOMODE0_MSSEL_CLR			(~(_SP0_SIOMODE0_MSSEL_MASK))

#define _SP0_SIOMODE0_RATE_SHIFT		(0)
#define _SP0_SIOMODE0_RATE_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _SP0_SIOMODE0_RATE_MASK			(_SP0_SIOMODE0_RATE_MK(0x00ffu))
#define _SP0_SIOMODE0_RATE_CLR			(~(_SP0_SIOMODE0_RATE_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 DMATRG0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_DMATRG0_GET()			_REG_GET(_SP0_DMATRG0_ADDR)
#define _SP0_DMATRG0_SET(Val)			_REG_SET(_SP0_DMATRG0_ADDR, Val)
#define _SP0_DMATRG0_AOI(AND,OR,INV)		_REG_AOI(_SP0_DMATRG0_ADDR,AND,OR,INV)
#define _SP0_DMATRG0_FGET(Field)			_FIELD_GET(_SP0_DMATRG0_ADDR, _SP0_DMATRG0_##Field##)
#define _SP0_DMATRG0_FSET(Field, Val)		_FIELD_SET(_SP0_DMATRG0_ADDR, _SP0_DMATRG0_##Field##, Val)
#define _SP0_DMATRG0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_DMATRG0_ADDR, _SP0_DMATRG0_##Field##, AND, OR, INV)

#define _SP0_DMATRG0_TRG_SHIFT		(0)
#define _SP0_DMATRG0_TRG_MK(n)		((Uint16)(n) & 0x0001u) 
#define _SP0_DMATRG0_TRG_MASK			(_SP0_DMATRG0_TRG_MK(0x0001u))
#define _SP0_DMATRG0_TRG_CLR			(~(_SP0_DMATRG0_TRG_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 DMAMODE0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_DMAMODE0_GET()			_REG_GET(_SP0_DMAMODE0_ADDR)
#define _SP0_DMAMODE0_SET(Val)			_REG_SET(_SP0_DMAMODE0_ADDR, Val)
#define _SP0_DMAMODE0_AOI(AND,OR,INV)		_REG_AOI(_SP0_DMAMODE0_ADDR,AND,OR,INV)
#define _SP0_DMAMODE0_FGET(Field)			_FIELD_GET(_SP0_DMAMODE0_ADDR, _SP0_DMAMODE0_##Field##)
#define _SP0_DMAMODE0_FSET(Field, Val)		_FIELD_SET(_SP0_DMAMODE0_ADDR, _SP0_DMAMODE0_##Field##, Val)
#define _SP0_DMAMODE0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_DMAMODE0_ADDR, _SP0_DMAMODE0_##Field##, AND, OR, INV)

#define _SP0_DMAMODE0_PRM_SHIFT		(12)
#define _SP0_DMAMODE0_PRM_MK(n)		(((Uint16)(n) & 0x0003u) << _SP0_DMAMODE0_PRM_SHIFT)
#define _SP0_DMAMODE0_PRM_MASK			(_SP0_DMAMODE0_PRM_MK(0x0003u))
#define _SP0_DMAMODE0_PRM_CLR			(~(_SP0_DMAMODE0_PRM_MASK))

#define _SP0_DMAMODE0_DIR_SHIFT		(11)
#define _SP0_DMAMODE0_DIR_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_DMAMODE0_DIR_SHIFT)
#define _SP0_DMAMODE0_DIR_MASK			(_SP0_DMAMODE0_DIR_MK(0x0001u))
#define _SP0_DMAMODE0_DIR_CLR			(~(_SP0_DMAMODE0_DIR_MASK))

#define _SP0_DMAMODE0_TRSZ_SHIFT		(0)
#define _SP0_DMAMODE0_TRSZ_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _SP0_DMAMODE0_TRSZ_MASK			(_SP0_DMAMODE0_TRSZ_MK(0x07ffu))
#define _SP0_DMAMODE0_TRSZ_CLR			(~(_SP0_DMAMODE0_TRSZ_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 DMASTADL0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_DMASTADL0_GET()			_REG_GET(_SP0_DMASTADL0_ADDR)
#define _SP0_DMASTADL0_SET(Val)			_REG_SET(_SP0_DMASTADL0_ADDR, Val)
#define _SP0_DMASTADL0_AOI(AND,OR,INV)		_REG_AOI(_SP0_DMASTADL0_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for SP0 DMASTADH0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_DMASTADH0_GET()			_REG_GET(_SP0_DMASTADH0_ADDR)
#define _SP0_DMASTADH0_SET(Val)			_REG_SET(_SP0_DMASTADH0_ADDR, Val)
#define _SP0_DMASTADH0_AOI(AND,OR,INV)		_REG_AOI(_SP0_DMASTADH0_ADDR,AND,OR,INV)
#define _SP0_DMASTADH0_FGET(Field)			_FIELD_GET(_SP0_DMASTADH0_ADDR, _SP0_DMASTADH0_##Field##)
#define _SP0_DMASTADH0_FSET(Field, Val)		_FIELD_SET(_SP0_DMASTADH0_ADDR, _SP0_DMASTADH0_##Field##, Val)
#define _SP0_DMASTADH0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_DMASTADH0_ADDR, _SP0_DMASTADH0_##Field##, AND, OR, INV)

#define _SP0_DMASTADH0_ADRH_SHIFT		(0)
#define _SP0_DMASTADH0_ADRH_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _SP0_DMASTADH0_ADRH_MASK			(_SP0_DMASTADH0_ADRH_MK(0x07ffu))
#define _SP0_DMASTADH0_ADRH_CLR			(~(_SP0_DMASTADH0_ADRH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP0 DMASTAT0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP0_DMASTAT0_GET()			_REG_GET(_SP0_DMASTAT0_ADDR)
#define _SP0_DMASTAT0_SET(Val)			_REG_SET(_SP0_DMASTAT0_ADDR, Val)
#define _SP0_DMASTAT0_AOI(AND,OR,INV)		_REG_AOI(_SP0_DMASTAT0_ADDR,AND,OR,INV)
#define _SP0_DMASTAT0_FGET(Field)			_FIELD_GET(_SP0_DMASTAT0_ADDR, _SP0_DMASTAT0_##Field##)
#define _SP0_DMASTAT0_FSET(Field, Val)		_FIELD_SET(_SP0_DMASTAT0_ADDR, _SP0_DMASTAT0_##Field##, Val)
#define _SP0_DMASTAT0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP0_DMASTAT0_ADDR, _SP0_DMASTAT0_##Field##, AND, OR, INV)

#define _SP0_DMASTAT0_RUN_SHIFT		(15)
#define _SP0_DMASTAT0_RUN_MK(n)		(((Uint16)(n) & 0x0001u) << _SP0_DMASTAT0_RUN_SHIFT)
#define _SP0_DMASTAT0_RUN_MASK			(_SP0_DMASTAT0_RUN_MK(0x0001u))
#define _SP0_DMASTAT0_RUN_CLR			(~(_SP0_DMASTAT0_RUN_MASK))

#define _SP0_DMASTAT0_REM_SHIFT		(0)
#define _SP0_DMASTAT0_REM_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _SP0_DMASTAT0_REM_MASK			(_SP0_DMASTAT0_REM_MK(0x07ffu))
#define _SP0_DMASTAT0_REM_CLR			(~(_SP0_DMASTAT0_REM_MASK))