csl_sp1hal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... SP1 - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_sp1hal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for SP1:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for SP1 TXDATA1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP1_TXDATA1_GET()			_REG_GET(_SP1_TXDATA1_ADDR)
#define _SP1_TXDATA1_SET(Val)			_REG_SET(_SP1_TXDATA1_ADDR, Val)
#define _SP1_TXDATA1_AOI(AND,OR,INV)		_REG_AOI(_SP1_TXDATA1_ADDR,AND,OR,INV)
#define _SP1_TXDATA1_FGET(Field)			_FIELD_GET(_SP1_TXDATA1_ADDR, _SP1_TXDATA1_##Field##)
#define _SP1_TXDATA1_FSET(Field, Val)		_FIELD_SET(_SP1_TXDATA1_ADDR, _SP1_TXDATA1_##Field##, Val)
#define _SP1_TXDATA1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP1_TXDATA1_ADDR, _SP1_TXDATA1_##Field##, AND, OR, INV)

#define _SP1_TXDATA1_TXD_SHIFT		(0)
#define _SP1_TXDATA1_TXD_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _SP1_TXDATA1_TXD_MASK			(_SP1_TXDATA1_TXD_MK(0x00ffu))
#define _SP1_TXDATA1_TXD_CLR			(~(_SP1_TXDATA1_TXD_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP1 RXDATA1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP1_RXDATA1_GET()			_REG_GET(_SP1_RXDATA1_ADDR)
#define _SP1_RXDATA1_SET(Val)			_REG_SET(_SP1_RXDATA1_ADDR, Val)
#define _SP1_RXDATA1_AOI(AND,OR,INV)		_REG_AOI(_SP1_RXDATA1_ADDR,AND,OR,INV)
#define _SP1_RXDATA1_FGET(Field)			_FIELD_GET(_SP1_RXDATA1_ADDR, _SP1_RXDATA1_##Field##)
#define _SP1_RXDATA1_FSET(Field, Val)		_FIELD_SET(_SP1_RXDATA1_ADDR, _SP1_RXDATA1_##Field##, Val)
#define _SP1_RXDATA1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP1_RXDATA1_ADDR, _SP1_RXDATA1_##Field##, AND, OR, INV)

#define _SP1_RXDATA1_XMIT_SHIFT		(8)
#define _SP1_RXDATA1_XMIT_MK(n)		(((Uint16)(n) & 0x0001u) << _SP1_RXDATA1_XMIT_SHIFT)
#define _SP1_RXDATA1_XMIT_MASK			(_SP1_RXDATA1_XMIT_MK(0x0001u))
#define _SP1_RXDATA1_XMIT_CLR			(~(_SP1_RXDATA1_XMIT_MASK))

#define _SP1_RXDATA1_RXD_SHIFT		(0)
#define _SP1_RXDATA1_RXD_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _SP1_RXDATA1_RXD_MASK			(_SP1_RXDATA1_RXD_MK(0x00ffu))
#define _SP1_RXDATA1_RXD_CLR			(~(_SP1_RXDATA1_RXD_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP1 SIOEN1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP1_SIOEN1_GET()			_REG_GET(_SP1_SIOEN1_ADDR)
#define _SP1_SIOEN1_SET(Val)			_REG_SET(_SP1_SIOEN1_ADDR, Val)
#define _SP1_SIOEN1_AOI(AND,OR,INV)		_REG_AOI(_SP1_SIOEN1_ADDR,AND,OR,INV)
#define _SP1_SIOEN1_FGET(Field)			_FIELD_GET(_SP1_SIOEN1_ADDR, _SP1_SIOEN1_##Field##)
#define _SP1_SIOEN1_FSET(Field, Val)		_FIELD_SET(_SP1_SIOEN1_ADDR, _SP1_SIOEN1_##Field##, Val)
#define _SP1_SIOEN1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP1_SIOEN1_ADDR, _SP1_SIOEN1_##Field##, AND, OR, INV)

#define _SP1_SIOEN1_SIOEN_SHIFT		(0)
#define _SP1_SIOEN1_SIOEN_MK(n)		((Uint16)(n) & 0x0001u) 
#define _SP1_SIOEN1_SIOEN_MASK			(_SP1_SIOEN1_SIOEN_MK(0x0001u))
#define _SP1_SIOEN1_SIOEN_CLR			(~(_SP1_SIOEN1_SIOEN_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for SP1 SIOMODE1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _SP1_SIOMODE1_GET()			_REG_GET(_SP1_SIOMODE1_ADDR)
#define _SP1_SIOMODE1_SET(Val)			_REG_SET(_SP1_SIOMODE1_ADDR, Val)
#define _SP1_SIOMODE1_AOI(AND,OR,INV)		_REG_AOI(_SP1_SIOMODE1_ADDR,AND,OR,INV)
#define _SP1_SIOMODE1_FGET(Field)			_FIELD_GET(_SP1_SIOMODE1_ADDR, _SP1_SIOMODE1_##Field##)
#define _SP1_SIOMODE1_FSET(Field, Val)		_FIELD_SET(_SP1_SIOMODE1_ADDR, _SP1_SIOMODE1_##Field##, Val)
#define _SP1_SIOMODE1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_SP1_SIOMODE1_ADDR, _SP1_SIOMODE1_##Field##, AND, OR, INV)

#define _SP1_SIOMODE1_SLVEN_SHIFT		(12)
#define _SP1_SIOMODE1_SLVEN_MK(n)		(((Uint16)(n) & 0x0001u) << _SP1_SIOMODE1_SLVEN_SHIFT)
#define _SP1_SIOMODE1_SLVEN_MASK			(_SP1_SIOMODE1_SLVEN_MK(0x0001u))
#define _SP1_SIOMODE1_SLVEN_CLR			(~(_SP1_SIOMODE1_SLVEN_MASK))

#define _SP1_SIOMODE1_SIOCLR_SHIFT		(11)
#define _SP1_SIOMODE1_SIOCLR_MK(n)		(((Uint16)(n) & 0x0001u) << _SP1_SIOMODE1_SIOCLR_SHIFT)
#define _SP1_SIOMODE1_SIOCLR_MASK			(_SP1_SIOMODE1_SIOCLR_MK(0x0001u))
#define _SP1_SIOMODE1_SIOCLR_CLR			(~(_SP1_SIOMODE1_SIOCLR_MASK))

#define _SP1_SIOMODE1_SCLKM_SHIFT		(10)
#define _SP1_SIOMODE1_SCLKM_MK(n)		(((Uint16)(n) & 0x0001u) << _SP1_SIOMODE1_SCLKM_SHIFT)
#define _SP1_SIOMODE1_SCLKM_MASK			(_SP1_SIOMODE1_SCLKM_MK(0x0001u))
#define _SP1_SIOMODE1_SCLKM_CLR			(~(_SP1_SIOMODE1_SCLKM_MASK))

#define _SP1_SIOMODE1_MSB_SHIFT		(9)
#define _SP1_SIOMODE1_MSB_MK(n)		(((Uint16)(n) & 0x0001u) << _SP1_SIOMODE1_MSB_SHIFT)
#define _SP1_SIOMODE1_MSB_MASK			(_SP1_SIOMODE1_MSB_MK(0x0001u))
#define _SP1_SIOMODE1_MSB_CLR			(~(_SP1_SIOMODE1_MSB_MASK))

#define _SP1_SIOMODE1_MSSEL_SHIFT		(8)
#define _SP1_SIOMODE1_MSSEL_MK(n)		(((Uint16)(n) & 0x0001u) << _SP1_SIOMODE1_MSSEL_SHIFT)
#define _SP1_SIOMODE1_MSSEL_MASK			(_SP1_SIOMODE1_MSSEL_MK(0x0001u))
#define _SP1_SIOMODE1_MSSEL_CLR			(~(_SP1_SIOMODE1_MSSEL_MASK))

#define _SP1_SIOMODE1_RATE_SHIFT		(0)
#define _SP1_SIOMODE1_RATE_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _SP1_SIOMODE1_RATE_MASK			(_SP1_SIOMODE1_RATE_MK(0x00ffu))
#define _SP1_SIOMODE1_RATE_CLR			(~(_SP1_SIOMODE1_RATE_MASK))