csl_uart1hal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... UART1 - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_uart1hal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for UART1:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for UART1 DTRR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_DTRR1_GET()			_REG_GET(_UART1_DTRR1_ADDR)
#define _UART1_DTRR1_SET(Val)			_REG_SET(_UART1_DTRR1_ADDR, Val)
#define _UART1_DTRR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_DTRR1_ADDR,AND,OR,INV)
#define _UART1_DTRR1_FGET(Field)			_FIELD_GET(_UART1_DTRR1_ADDR, _UART1_DTRR1_##Field##)
#define _UART1_DTRR1_FSET(Field, Val)		_FIELD_SET(_UART1_DTRR1_ADDR, _UART1_DTRR1_##Field##, Val)
#define _UART1_DTRR1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART1_DTRR1_ADDR, _UART1_DTRR1_##Field##, AND, OR, INV)

#define _UART1_DTRR1_RVF_SHIFT		(12)
#define _UART1_DTRR1_RVF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_DTRR1_RVF_SHIFT)
#define _UART1_DTRR1_RVF_MASK			(_UART1_DTRR1_RVF_MK(0x0001u))
#define _UART1_DTRR1_RVF_CLR			(~(_UART1_DTRR1_RVF_MASK))

#define _UART1_DTRR1_BF_SHIFT		(11)
#define _UART1_DTRR1_BF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_DTRR1_BF_SHIFT)
#define _UART1_DTRR1_BF_MASK			(_UART1_DTRR1_BF_MK(0x0001u))
#define _UART1_DTRR1_BF_CLR			(~(_UART1_DTRR1_BF_MASK))

#define _UART1_DTRR1_FE_SHIFT		(10)
#define _UART1_DTRR1_FE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_DTRR1_FE_SHIFT)
#define _UART1_DTRR1_FE_MASK			(_UART1_DTRR1_FE_MK(0x0001u))
#define _UART1_DTRR1_FE_CLR			(~(_UART1_DTRR1_FE_MASK))

#define _UART1_DTRR1_ORF_SHIFT		(9)
#define _UART1_DTRR1_ORF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_DTRR1_ORF_SHIFT)
#define _UART1_DTRR1_ORF_MASK			(_UART1_DTRR1_ORF_MK(0x0001u))
#define _UART1_DTRR1_ORF_CLR			(~(_UART1_DTRR1_ORF_MASK))

#define _UART1_DTRR1_PEF_SHIFT		(8)
#define _UART1_DTRR1_PEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_DTRR1_PEF_SHIFT)
#define _UART1_DTRR1_PEF_MASK			(_UART1_DTRR1_PEF_MK(0x0001u))
#define _UART1_DTRR1_PEF_CLR			(~(_UART1_DTRR1_PEF_MASK))

#define _UART1_DTRR1_DTR_SHIFT		(0)
#define _UART1_DTRR1_DTR_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _UART1_DTRR1_DTR_MASK			(_UART1_DTRR1_DTR_MK(0x00ffu))
#define _UART1_DTRR1_DTR_CLR			(~(_UART1_DTRR1_DTR_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART1 BRSR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_BRSR1_GET()			_REG_GET(_UART1_BRSR1_ADDR)
#define _UART1_BRSR1_SET(Val)			_REG_SET(_UART1_BRSR1_ADDR, Val)
#define _UART1_BRSR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_BRSR1_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for UART1 MSR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_MSR1_GET()			_REG_GET(_UART1_MSR1_ADDR)
#define _UART1_MSR1_SET(Val)			_REG_SET(_UART1_MSR1_ADDR, Val)
#define _UART1_MSR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_MSR1_ADDR,AND,OR,INV)
#define _UART1_MSR1_FGET(Field)			_FIELD_GET(_UART1_MSR1_ADDR, _UART1_MSR1_##Field##)
#define _UART1_MSR1_FSET(Field, Val)		_FIELD_SET(_UART1_MSR1_ADDR, _UART1_MSR1_##Field##, Val)
#define _UART1_MSR1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART1_MSR1_ADDR, _UART1_MSR1_##Field##, AND, OR, INV)

#define _UART1_MSR1_RFTIE_SHIFT		(15)
#define _UART1_MSR1_RFTIE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_MSR1_RFTIE_SHIFT)
#define _UART1_MSR1_RFTIE_MASK			(_UART1_MSR1_RFTIE_MK(0x0001u))
#define _UART1_MSR1_RFTIE_CLR			(~(_UART1_MSR1_RFTIE_MASK))

#define _UART1_MSR1_TFTIE_SHIFT		(14)
#define _UART1_MSR1_TFTIE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_MSR1_TFTIE_SHIFT)
#define _UART1_MSR1_TFTIE_MASK			(_UART1_MSR1_TFTIE_MK(0x0001u))
#define _UART1_MSR1_TFTIE_CLR			(~(_UART1_MSR1_TFTIE_MASK))

#define _UART1_MSR1_REIE_SHIFT		(13)
#define _UART1_MSR1_REIE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_MSR1_REIE_SHIFT)
#define _UART1_MSR1_REIE_MASK			(_UART1_MSR1_REIE_MK(0x0001u))
#define _UART1_MSR1_REIE_CLR			(~(_UART1_MSR1_REIE_MASK))

#define _UART1_MSR1_TOIC_SHIFT		(10)
#define _UART1_MSR1_TOIC_MK(n)		(((Uint16)(n) & 0x0003u) << _UART1_MSR1_TOIC_SHIFT)
#define _UART1_MSR1_TOIC_MASK			(_UART1_MSR1_TOIC_MK(0x0003u))
#define _UART1_MSR1_TOIC_CLR			(~(_UART1_MSR1_TOIC_MASK))

#define _UART1_MSR1_PEB_SHIFT		(4)
#define _UART1_MSR1_PEB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_MSR1_PEB_SHIFT)
#define _UART1_MSR1_PEB_MASK			(_UART1_MSR1_PEB_MK(0x0001u))
#define _UART1_MSR1_PEB_CLR			(~(_UART1_MSR1_PEB_MASK))

#define _UART1_MSR1_PSB_SHIFT		(3)
#define _UART1_MSR1_PSB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_MSR1_PSB_SHIFT)
#define _UART1_MSR1_PSB_MASK			(_UART1_MSR1_PSB_MK(0x0001u))
#define _UART1_MSR1_PSB_CLR			(~(_UART1_MSR1_PSB_MASK))

#define _UART1_MSR1_SBLS_SHIFT		(2)
#define _UART1_MSR1_SBLS_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_MSR1_SBLS_SHIFT)
#define _UART1_MSR1_SBLS_MASK			(_UART1_MSR1_SBLS_MK(0x0001u))
#define _UART1_MSR1_SBLS_CLR			(~(_UART1_MSR1_SBLS_MASK))

#define _UART1_MSR1_CLS_SHIFT		(0)
#define _UART1_MSR1_CLS_MK(n)		((Uint16)(n) & 0x0001u) 
#define _UART1_MSR1_CLS_MASK			(_UART1_MSR1_CLS_MK(0x0001u))
#define _UART1_MSR1_CLS_CLR			(~(_UART1_MSR1_CLS_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART1 RFCR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_RFCR1_GET()			_REG_GET(_UART1_RFCR1_ADDR)
#define _UART1_RFCR1_SET(Val)			_REG_SET(_UART1_RFCR1_ADDR, Val)
#define _UART1_RFCR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_RFCR1_ADDR,AND,OR,INV)
#define _UART1_RFCR1_FGET(Field)			_FIELD_GET(_UART1_RFCR1_ADDR, _UART1_RFCR1_##Field##)
#define _UART1_RFCR1_FSET(Field, Val)		_FIELD_SET(_UART1_RFCR1_ADDR, _UART1_RFCR1_##Field##, Val)
#define _UART1_RFCR1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART1_RFCR1_ADDR, _UART1_RFCR1_##Field##, AND, OR, INV)

#define _UART1_RFCR1_RFCB_SHIFT		(15)
#define _UART1_RFCR1_RFCB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_RFCR1_RFCB_SHIFT)
#define _UART1_RFCR1_RFCB_MASK			(_UART1_RFCR1_RFCB_MK(0x0001u))
#define _UART1_RFCR1_RFCB_CLR			(~(_UART1_RFCR1_RFCB_MASK))

#define _UART1_RFCR1_RDEF_SHIFT		(14)
#define _UART1_RFCR1_RDEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_RFCR1_RDEF_SHIFT)
#define _UART1_RFCR1_RDEF_MASK			(_UART1_RFCR1_RDEF_MK(0x0001u))
#define _UART1_RFCR1_RDEF_CLR			(~(_UART1_RFCR1_RDEF_MASK))

#define _UART1_RFCR1_RTL_SHIFT		(8)
#define _UART1_RFCR1_RTL_MK(n)		(((Uint16)(n) & 0x0007u) << _UART1_RFCR1_RTL_SHIFT)
#define _UART1_RFCR1_RTL_MASK			(_UART1_RFCR1_RTL_MK(0x0007u))
#define _UART1_RFCR1_RTL_CLR			(~(_UART1_RFCR1_RTL_MASK))

#define _UART1_RFCR1_RWC_SHIFT		(0)
#define _UART1_RFCR1_RWC_MK(n)		((Uint16)(n) & 0x003fu) 
#define _UART1_RFCR1_RWC_MASK			(_UART1_RFCR1_RWC_MK(0x003fu))
#define _UART1_RFCR1_RWC_CLR			(~(_UART1_RFCR1_RWC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART1 TFCR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_TFCR1_GET()			_REG_GET(_UART1_TFCR1_ADDR)
#define _UART1_TFCR1_SET(Val)			_REG_SET(_UART1_TFCR1_ADDR, Val)
#define _UART1_TFCR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_TFCR1_ADDR,AND,OR,INV)
#define _UART1_TFCR1_FGET(Field)			_FIELD_GET(_UART1_TFCR1_ADDR, _UART1_TFCR1_##Field##)
#define _UART1_TFCR1_FSET(Field, Val)		_FIELD_SET(_UART1_TFCR1_ADDR, _UART1_TFCR1_##Field##, Val)
#define _UART1_TFCR1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART1_TFCR1_ADDR, _UART1_TFCR1_##Field##, AND, OR, INV)

#define _UART1_TFCR1_TFCB_SHIFT		(15)
#define _UART1_TFCR1_TFCB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_TFCR1_TFCB_SHIFT)
#define _UART1_TFCR1_TFCB_MASK			(_UART1_TFCR1_TFCB_MK(0x0001u))
#define _UART1_TFCR1_TFCB_CLR			(~(_UART1_TFCR1_TFCB_MASK))

#define _UART1_TFCR1_TTL_SHIFT		(8)
#define _UART1_TFCR1_TTL_MK(n)		(((Uint16)(n) & 0x0007u) << _UART1_TFCR1_TTL_SHIFT)
#define _UART1_TFCR1_TTL_MASK			(_UART1_TFCR1_TTL_MK(0x0007u))
#define _UART1_TFCR1_TTL_CLR			(~(_UART1_TFCR1_TTL_MASK))

#define _UART1_TFCR1_TWC_SHIFT		(0)
#define _UART1_TFCR1_TWC_MK(n)		((Uint16)(n) & 0x003fu) 
#define _UART1_TFCR1_TWC_MASK			(_UART1_TFCR1_TWC_MK(0x003fu))
#define _UART1_TFCR1_TWC_CLR			(~(_UART1_TFCR1_TWC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART1 LCR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_LCR1_GET()			_REG_GET(_UART1_LCR1_ADDR)
#define _UART1_LCR1_SET(Val)			_REG_SET(_UART1_LCR1_ADDR, Val)
#define _UART1_LCR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_LCR1_ADDR,AND,OR,INV)
#define _UART1_LCR1_FGET(Field)			_FIELD_GET(_UART1_LCR1_ADDR, _UART1_LCR1_##Field##)
#define _UART1_LCR1_FSET(Field, Val)		_FIELD_SET(_UART1_LCR1_ADDR, _UART1_LCR1_##Field##, Val)
#define _UART1_LCR1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART1_LCR1_ADDR, _UART1_LCR1_##Field##, AND, OR, INV)

#define _UART1_LCR1_UTST_SHIFT		(14)
#define _UART1_LCR1_UTST_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_LCR1_UTST_SHIFT)
#define _UART1_LCR1_UTST_MASK			(_UART1_LCR1_UTST_MK(0x0001u))
#define _UART1_LCR1_UTST_CLR			(~(_UART1_LCR1_UTST_MASK))

#define _UART1_LCR1_BOC_SHIFT		(8)
#define _UART1_LCR1_BOC_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_LCR1_BOC_SHIFT)
#define _UART1_LCR1_BOC_MASK			(_UART1_LCR1_BOC_MK(0x0001u))
#define _UART1_LCR1_BOC_CLR			(~(_UART1_LCR1_BOC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART1 SR1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART1_SR1_GET()			_REG_GET(_UART1_SR1_ADDR)
#define _UART1_SR1_SET(Val)			_REG_SET(_UART1_SR1_ADDR, Val)
#define _UART1_SR1_AOI(AND,OR,INV)		_REG_AOI(_UART1_SR1_ADDR,AND,OR,INV)
#define _UART1_SR1_FGET(Field)			_FIELD_GET(_UART1_SR1_ADDR, _UART1_SR1_##Field##)
#define _UART1_SR1_FSET(Field, Val)		_FIELD_SET(_UART1_SR1_ADDR, _UART1_SR1_##Field##, Val)
#define _UART1_SR1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART1_SR1_ADDR, _UART1_SR1_##Field##, AND, OR, INV)

#define _UART1_SR1_RFTI_SHIFT		(11)
#define _UART1_SR1_RFTI_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_SR1_RFTI_SHIFT)
#define _UART1_SR1_RFTI_MASK			(_UART1_SR1_RFTI_MK(0x0001u))
#define _UART1_SR1_RFTI_CLR			(~(_UART1_SR1_RFTI_MASK))

#define _UART1_SR1_TFTI_SHIFT		(10)
#define _UART1_SR1_TFTI_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_SR1_TFTI_SHIFT)
#define _UART1_SR1_TFTI_MASK			(_UART1_SR1_TFTI_MK(0x0001u))
#define _UART1_SR1_TFTI_CLR			(~(_UART1_SR1_TFTI_MASK))

#define _UART1_SR1_RFER_SHIFT		(9)
#define _UART1_SR1_RFER_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_SR1_RFER_SHIFT)
#define _UART1_SR1_RFER_MASK			(_UART1_SR1_RFER_MK(0x0001u))
#define _UART1_SR1_RFER_CLR			(~(_UART1_SR1_RFER_MASK))

#define _UART1_SR1_TOIF_SHIFT		(8)
#define _UART1_SR1_TOIF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_SR1_TOIF_SHIFT)
#define _UART1_SR1_TOIF_MASK			(_UART1_SR1_TOIF_MK(0x0001u))
#define _UART1_SR1_TOIF_CLR			(~(_UART1_SR1_TOIF_MASK))

#define _UART1_SR1_RFNEF_SHIFT		(2)
#define _UART1_SR1_RFNEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_SR1_RFNEF_SHIFT)
#define _UART1_SR1_RFNEF_MASK			(_UART1_SR1_RFNEF_MK(0x0001u))
#define _UART1_SR1_RFNEF_CLR			(~(_UART1_SR1_RFNEF_MASK))

#define _UART1_SR1_TFEF_SHIFT		(1)
#define _UART1_SR1_TFEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART1_SR1_TFEF_SHIFT)
#define _UART1_SR1_TFEF_MASK			(_UART1_SR1_TFEF_MK(0x0001u))
#define _UART1_SR1_TFEF_CLR			(~(_UART1_SR1_TFEF_MASK))

#define _UART1_SR1_TREF_SHIFT		(0)
#define _UART1_SR1_TREF_MK(n)		((Uint16)(n) & 0x0001u) 
#define _UART1_SR1_TREF_MASK			(_UART1_SR1_TREF_MK(0x0001u))
#define _UART1_SR1_TREF_CLR			(~(_UART1_SR1_TREF_MASK))