csl_h3ahal_270.h

dm270 source code

#define _H3A_AFCOEFF29_FGET(Field)			_FIELD_GET(_H3A_AFCOEFF29_ADDR, _H3A_AFCOEFF29_##Field##)
#define _H3A_AFCOEFF29_FSET(Field, Val)		_FIELD_SET(_H3A_AFCOEFF29_ADDR, _H3A_AFCOEFF29_##Field##, Val)
#define _H3A_AFCOEFF29_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFCOEFF29_ADDR, _H3A_AFCOEFF29_##Field##, AND, OR, INV)

#define _H3A_AFCOEFF29_COEFF29_SHIFT		(0)
#define _H3A_AFCOEFF29_COEFF29_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _H3A_AFCOEFF29_COEFF29_MASK			(_H3A_AFCOEFF29_COEFF29_MK(0x07ffu))
#define _H3A_AFCOEFF29_COEFF29_CLR			(~(_H3A_AFCOEFF29_COEFF29_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFCOEFF210 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFCOEFF210_GET()			_REG_GET(_H3A_AFCOEFF210_ADDR)
#define _H3A_AFCOEFF210_SET(Val)			_REG_SET(_H3A_AFCOEFF210_ADDR, Val)
#define _H3A_AFCOEFF210_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFCOEFF210_ADDR,AND,OR,INV)
#define _H3A_AFCOEFF210_FGET(Field)			_FIELD_GET(_H3A_AFCOEFF210_ADDR, _H3A_AFCOEFF210_##Field##)
#define _H3A_AFCOEFF210_FSET(Field, Val)		_FIELD_SET(_H3A_AFCOEFF210_ADDR, _H3A_AFCOEFF210_##Field##, Val)
#define _H3A_AFCOEFF210_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFCOEFF210_ADDR, _H3A_AFCOEFF210_##Field##, AND, OR, INV)

#define _H3A_AFCOEFF210_COEFF210_SHIFT		(0)
#define _H3A_AFCOEFF210_COEFF210_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _H3A_AFCOEFF210_COEFF210_MASK			(_H3A_AFCOEFF210_COEFF210_MK(0x07ffu))
#define _H3A_AFCOEFF210_COEFF210_CLR			(~(_H3A_AFCOEFF210_COEFF210_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWCTRL register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWCTRL_GET()			_REG_GET(_H3A_AEWCTRL_ADDR)
#define _H3A_AEWCTRL_SET(Val)			_REG_SET(_H3A_AEWCTRL_ADDR, Val)
#define _H3A_AEWCTRL_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWCTRL_ADDR,AND,OR,INV)
#define _H3A_AEWCTRL_FGET(Field)			_FIELD_GET(_H3A_AEWCTRL_ADDR, _H3A_AEWCTRL_##Field##)
#define _H3A_AEWCTRL_FSET(Field, Val)		_FIELD_SET(_H3A_AEWCTRL_ADDR, _H3A_AEWCTRL_##Field##, Val)
#define _H3A_AEWCTRL_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWCTRL_ADDR, _H3A_AEWCTRL_##Field##, AND, OR, INV)

#define _H3A_AEWCTRL_AVE2LMT_SHIFT		(0)
#define _H3A_AEWCTRL_AVE2LMT_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _H3A_AEWCTRL_AVE2LMT_MASK			(_H3A_AEWCTRL_AVE2LMT_MK(0x00ffu))
#define _H3A_AEWCTRL_AVE2LMT_CLR			(~(_H3A_AEWCTRL_AVE2LMT_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWWIN1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWWIN1_GET()			_REG_GET(_H3A_AEWWIN1_ADDR)
#define _H3A_AEWWIN1_SET(Val)			_REG_SET(_H3A_AEWWIN1_ADDR, Val)
#define _H3A_AEWWIN1_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWWIN1_ADDR,AND,OR,INV)
#define _H3A_AEWWIN1_FGET(Field)			_FIELD_GET(_H3A_AEWWIN1_ADDR, _H3A_AEWWIN1_##Field##)
#define _H3A_AEWWIN1_FSET(Field, Val)		_FIELD_SET(_H3A_AEWWIN1_ADDR, _H3A_AEWWIN1_##Field##, Val)
#define _H3A_AEWWIN1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWWIN1_ADDR, _H3A_AEWWIN1_##Field##, AND, OR, INV)

#define _H3A_AEWWIN1_WINV_SHIFT		(8)
#define _H3A_AEWWIN1_WINV_MK(n)		(((Uint16)(n) & 0x001fu) << _H3A_AEWWIN1_WINV_SHIFT)
#define _H3A_AEWWIN1_WINV_MASK			(_H3A_AEWWIN1_WINV_MK(0x001fu))
#define _H3A_AEWWIN1_WINV_CLR			(~(_H3A_AEWWIN1_WINV_MASK))

#define _H3A_AEWWIN1_WINH_SHIFT		(0)
#define _H3A_AEWWIN1_WINH_MK(n)		((Uint16)(n) & 0x007fu) 
#define _H3A_AEWWIN1_WINH_MASK			(_H3A_AEWWIN1_WINH_MK(0x007fu))
#define _H3A_AEWWIN1_WINH_CLR			(~(_H3A_AEWWIN1_WINH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWWIN2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWWIN2_GET()			_REG_GET(_H3A_AEWWIN2_ADDR)
#define _H3A_AEWWIN2_SET(Val)			_REG_SET(_H3A_AEWWIN2_ADDR, Val)
#define _H3A_AEWWIN2_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWWIN2_ADDR,AND,OR,INV)
#define _H3A_AEWWIN2_FGET(Field)			_FIELD_GET(_H3A_AEWWIN2_ADDR, _H3A_AEWWIN2_##Field##)
#define _H3A_AEWWIN2_FSET(Field, Val)		_FIELD_SET(_H3A_AEWWIN2_ADDR, _H3A_AEWWIN2_##Field##, Val)
#define _H3A_AEWWIN2_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWWIN2_ADDR, _H3A_AEWWIN2_##Field##, AND, OR, INV)

#define _H3A_AEWWIN2_WINVC_SHIFT		(8)
#define _H3A_AEWWIN2_WINVC_MK(n)		(((Uint16)(n) & 0x0007u) << _H3A_AEWWIN2_WINVC_SHIFT)
#define _H3A_AEWWIN2_WINVC_MASK			(_H3A_AEWWIN2_WINVC_MK(0x0007u))
#define _H3A_AEWWIN2_WINVC_CLR			(~(_H3A_AEWWIN2_WINVC_MASK))

#define _H3A_AEWWIN2_WINHC_SHIFT		(0)
#define _H3A_AEWWIN2_WINHC_MK(n)		((Uint16)(n) & 0x000fu) 
#define _H3A_AEWWIN2_WINHC_MASK			(_H3A_AEWWIN2_WINHC_MK(0x000fu))
#define _H3A_AEWWIN2_WINHC_CLR			(~(_H3A_AEWWIN2_WINHC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWWIN3 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWWIN3_GET()			_REG_GET(_H3A_AEWWIN3_ADDR)
#define _H3A_AEWWIN3_SET(Val)			_REG_SET(_H3A_AEWWIN3_ADDR, Val)
#define _H3A_AEWWIN3_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWWIN3_ADDR,AND,OR,INV)
#define _H3A_AEWWIN3_FGET(Field)			_FIELD_GET(_H3A_AEWWIN3_ADDR, _H3A_AEWWIN3_##Field##)
#define _H3A_AEWWIN3_FSET(Field, Val)		_FIELD_SET(_H3A_AEWWIN3_ADDR, _H3A_AEWWIN3_##Field##, Val)
#define _H3A_AEWWIN3_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWWIN3_ADDR, _H3A_AEWWIN3_##Field##, AND, OR, INV)

#define _H3A_AEWWIN3_WINSH_SHIFT		(0)
#define _H3A_AEWWIN3_WINSH_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _H3A_AEWWIN3_WINSH_MASK			(_H3A_AEWWIN3_WINSH_MK(0x07ffu))
#define _H3A_AEWWIN3_WINSH_CLR			(~(_H3A_AEWWIN3_WINSH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWWIN4 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWWIN4_GET()			_REG_GET(_H3A_AEWWIN4_ADDR)
#define _H3A_AEWWIN4_SET(Val)			_REG_SET(_H3A_AEWWIN4_ADDR, Val)
#define _H3A_AEWWIN4_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWWIN4_ADDR,AND,OR,INV)
#define _H3A_AEWWIN4_FGET(Field)			_FIELD_GET(_H3A_AEWWIN4_ADDR, _H3A_AEWWIN4_##Field##)
#define _H3A_AEWWIN4_FSET(Field, Val)		_FIELD_SET(_H3A_AEWWIN4_ADDR, _H3A_AEWWIN4_##Field##, Val)
#define _H3A_AEWWIN4_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWWIN4_ADDR, _H3A_AEWWIN4_##Field##, AND, OR, INV)

#define _H3A_AEWWIN4_WINSV_SHIFT		(0)
#define _H3A_AEWWIN4_WINSV_MK(n)		((Uint16)(n) & 0x07ffu) 
#define _H3A_AEWWIN4_WINSV_MASK			(_H3A_AEWWIN4_WINSV_MK(0x07ffu))
#define _H3A_AEWWIN4_WINSV_CLR			(~(_H3A_AEWWIN4_WINSV_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWWIN5 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWWIN5_GET()			_REG_GET(_H3A_AEWWIN5_ADDR)
#define _H3A_AEWWIN5_SET(Val)			_REG_SET(_H3A_AEWWIN5_ADDR, Val)
#define _H3A_AEWWIN5_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWWIN5_ADDR,AND,OR,INV)
#define _H3A_AEWWIN5_FGET(Field)			_FIELD_GET(_H3A_AEWWIN5_ADDR, _H3A_AEWWIN5_##Field##)
#define _H3A_AEWWIN5_FSET(Field, Val)		_FIELD_SET(_H3A_AEWWIN5_ADDR, _H3A_AEWWIN5_##Field##, Val)
#define _H3A_AEWWIN5_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWWIN5_ADDR, _H3A_AEWWIN5_##Field##, AND, OR, INV)

#define _H3A_AEWWIN5_AEWINCV_SHIFT		(8)
#define _H3A_AEWWIN5_AEWINCV_MK(n)		(((Uint16)(n) & 0x000fu) << _H3A_AEWWIN5_AEWINCV_SHIFT)
#define _H3A_AEWWIN5_AEWINCV_MASK			(_H3A_AEWWIN5_AEWINCV_MK(0x000fu))
#define _H3A_AEWWIN5_AEWINCV_CLR			(~(_H3A_AEWWIN5_AEWINCV_MASK))

#define _H3A_AEWWIN5_AEWINCH_SHIFT		(0)
#define _H3A_AEWWIN5_AEWINCH_MK(n)		((Uint16)(n) & 0x000fu) 
#define _H3A_AEWWIN5_AEWINCH_MASK			(_H3A_AEWWIN5_AEWINCH_MK(0x000fu))
#define _H3A_AEWWIN5_AEWINCH_CLR			(~(_H3A_AEWWIN5_AEWINCH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWSDRA1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWSDRA1_GET()			_REG_GET(_H3A_AEWSDRA1_ADDR)
#define _H3A_AEWSDRA1_SET(Val)			_REG_SET(_H3A_AEWSDRA1_ADDR, Val)
#define _H3A_AEWSDRA1_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWSDRA1_ADDR,AND,OR,INV)
#define _H3A_AEWSDRA1_FGET(Field)			_FIELD_GET(_H3A_AEWSDRA1_ADDR, _H3A_AEWSDRA1_##Field##)
#define _H3A_AEWSDRA1_FSET(Field, Val)		_FIELD_SET(_H3A_AEWSDRA1_ADDR, _H3A_AEWSDRA1_##Field##, Val)
#define _H3A_AEWSDRA1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWSDRA1_ADDR, _H3A_AEWSDRA1_##Field##, AND, OR, INV)

#define _H3A_AEWSDRA1_ADRH_SHIFT		(0)
#define _H3A_AEWSDRA1_ADRH_MK(n)		((Uint16)(n) & 0x003fu) 
#define _H3A_AEWSDRA1_ADRH_MASK			(_H3A_AEWSDRA1_ADRH_MK(0x003fu))
#define _H3A_AEWSDRA1_ADRH_CLR			(~(_H3A_AEWSDRA1_ADRH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWSDRA2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWSDRA2_GET()			_REG_GET(_H3A_AEWSDRA2_ADDR)
#define _H3A_AEWSDRA2_SET(Val)			_REG_SET(_H3A_AEWSDRA2_ADDR, Val)
#define _H3A_AEWSDRA2_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWSDRA2_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for H3A AEWSDRFLG register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AEWSDRFLG_GET()			_REG_GET(_H3A_AEWSDRFLG_ADDR)
#define _H3A_AEWSDRFLG_SET(Val)			_REG_SET(_H3A_AEWSDRFLG_ADDR, Val)
#define _H3A_AEWSDRFLG_AOI(AND,OR,INV)		_REG_AOI(_H3A_AEWSDRFLG_ADDR,AND,OR,INV)
#define _H3A_AEWSDRFLG_FGET(Field)			_FIELD_GET(_H3A_AEWSDRFLG_ADDR, _H3A_AEWSDRFLG_##Field##)
#define _H3A_AEWSDRFLG_FSET(Field, Val)		_FIELD_SET(_H3A_AEWSDRFLG_ADDR, _H3A_AEWSDRFLG_##Field##, Val)
#define _H3A_AEWSDRFLG_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AEWSDRFLG_ADDR, _H3A_AEWSDRFLG_##Field##, AND, OR, INV)

#define _H3A_AEWSDRFLG_AEWSDRFLG_SHIFT		(0)
#define _H3A_AEWSDRFLG_AEWSDRFLG_MK(n)		((Uint16)(n) & 0x0001u) 
#define _H3A_AEWSDRFLG_AEWSDRFLG_MASK			(_H3A_AEWSDRFLG_AEWSDRFLG_MK(0x0001u))
#define _H3A_AEWSDRFLG_AEWSDRFLG_CLR			(~(_H3A_AEWSDRFLG_AEWSDRFLG_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A TEST3A register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_TEST3A_GET()			_REG_GET(_H3A_TEST3A_ADDR)
#define _H3A_TEST3A_SET(Val)			_REG_SET(_H3A_TEST3A_ADDR, Val)
#define _H3A_TEST3A_AOI(AND,OR,INV)		_REG_AOI(_H3A_TEST3A_ADDR,AND,OR,INV)