csl_h3ahal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... H3A - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_h3ahal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for H3A:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for H3A H3ACTRL register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_H3ACTRL_GET()			_REG_GET(_H3A_H3ACTRL_ADDR)
#define _H3A_H3ACTRL_SET(Val)			_REG_SET(_H3A_H3ACTRL_ADDR, Val)
#define _H3A_H3ACTRL_AOI(AND,OR,INV)		_REG_AOI(_H3A_H3ACTRL_ADDR,AND,OR,INV)
#define _H3A_H3ACTRL_FGET(Field)			_FIELD_GET(_H3A_H3ACTRL_ADDR, _H3A_H3ACTRL_##Field##)
#define _H3A_H3ACTRL_FSET(Field, Val)		_FIELD_SET(_H3A_H3ACTRL_ADDR, _H3A_H3ACTRL_##Field##, Val)
#define _H3A_H3ACTRL_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_H3ACTRL_ADDR, _H3A_H3ACTRL_##Field##, AND, OR, INV)

#define _H3A_H3ACTRL_AEWEN_SHIFT		(4)
#define _H3A_H3ACTRL_AEWEN_MK(n)		(((Uint16)(n) & 0x0001u) << _H3A_H3ACTRL_AEWEN_SHIFT)
#define _H3A_H3ACTRL_AEWEN_MASK			(_H3A_H3ACTRL_AEWEN_MK(0x0001u))
#define _H3A_H3ACTRL_AEWEN_CLR			(~(_H3A_H3ACTRL_AEWEN_MASK))

#define _H3A_H3ACTRL_AFEN_SHIFT		(0)
#define _H3A_H3ACTRL_AFEN_MK(n)		((Uint16)(n) & 0x0001u) 
#define _H3A_H3ACTRL_AFEN_MASK			(_H3A_H3ACTRL_AFEN_MK(0x0001u))
#define _H3A_H3ACTRL_AFEN_CLR			(~(_H3A_H3ACTRL_AFEN_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFCTRL register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFCTRL_GET()			_REG_GET(_H3A_AFCTRL_ADDR)
#define _H3A_AFCTRL_SET(Val)			_REG_SET(_H3A_AFCTRL_ADDR, Val)
#define _H3A_AFCTRL_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFCTRL_ADDR,AND,OR,INV)
#define _H3A_AFCTRL_FGET(Field)			_FIELD_GET(_H3A_AFCTRL_ADDR, _H3A_AFCTRL_##Field##)
#define _H3A_AFCTRL_FSET(Field, Val)		_FIELD_SET(_H3A_AFCTRL_ADDR, _H3A_AFCTRL_##Field##, Val)
#define _H3A_AFCTRL_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFCTRL_ADDR, _H3A_AFCTRL_##Field##, AND, OR, INV)

#define _H3A_AFCTRL_FVMODE_SHIFT		(4)
#define _H3A_AFCTRL_FVMODE_MK(n)		(((Uint16)(n) & 0x0001u) << _H3A_AFCTRL_FVMODE_SHIFT)
#define _H3A_AFCTRL_FVMODE_MASK			(_H3A_AFCTRL_FVMODE_MK(0x0001u))
#define _H3A_AFCTRL_FVMODE_CLR			(~(_H3A_AFCTRL_FVMODE_MASK))

#define _H3A_AFCTRL_GPOSUL_SHIFT		(3)
#define _H3A_AFCTRL_GPOSUL_MK(n)		(((Uint16)(n) & 0x0001u) << _H3A_AFCTRL_GPOSUL_SHIFT)
#define _H3A_AFCTRL_GPOSUL_MASK			(_H3A_AFCTRL_GPOSUL_MK(0x0001u))
#define _H3A_AFCTRL_GPOSUL_CLR			(~(_H3A_AFCTRL_GPOSUL_MASK))

#define _H3A_AFCTRL_GPOSUR_SHIFT		(2)
#define _H3A_AFCTRL_GPOSUR_MK(n)		(((Uint16)(n) & 0x0001u) << _H3A_AFCTRL_GPOSUR_SHIFT)
#define _H3A_AFCTRL_GPOSUR_MASK			(_H3A_AFCTRL_GPOSUR_MK(0x0001u))
#define _H3A_AFCTRL_GPOSUR_CLR			(~(_H3A_AFCTRL_GPOSUR_MASK))

#define _H3A_AFCTRL_GPOSLL_SHIFT		(1)
#define _H3A_AFCTRL_GPOSLL_MK(n)		(((Uint16)(n) & 0x0001u) << _H3A_AFCTRL_GPOSLL_SHIFT)
#define _H3A_AFCTRL_GPOSLL_MASK			(_H3A_AFCTRL_GPOSLL_MK(0x0001u))
#define _H3A_AFCTRL_GPOSLL_CLR			(~(_H3A_AFCTRL_GPOSLL_MASK))

#define _H3A_AFCTRL_GPOSLR_SHIFT		(0)
#define _H3A_AFCTRL_GPOSLR_MK(n)		((Uint16)(n) & 0x0001u) 
#define _H3A_AFCTRL_GPOSLR_MASK			(_H3A_AFCTRL_GPOSLR_MK(0x0001u))
#define _H3A_AFCTRL_GPOSLR_CLR			(~(_H3A_AFCTRL_GPOSLR_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFPAX1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFPAX1_GET()			_REG_GET(_H3A_AFPAX1_ADDR)
#define _H3A_AFPAX1_SET(Val)			_REG_SET(_H3A_AFPAX1_ADDR, Val)
#define _H3A_AFPAX1_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFPAX1_ADDR,AND,OR,INV)
#define _H3A_AFPAX1_FGET(Field)			_FIELD_GET(_H3A_AFPAX1_ADDR, _H3A_AFPAX1_##Field##)
#define _H3A_AFPAX1_FSET(Field, Val)		_FIELD_SET(_H3A_AFPAX1_ADDR, _H3A_AFPAX1_##Field##, Val)
#define _H3A_AFPAX1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFPAX1_ADDR, _H3A_AFPAX1_##Field##, AND, OR, INV)

#define _H3A_AFPAX1_PAXV_SHIFT		(8)
#define _H3A_AFPAX1_PAXV_MK(n)		(((Uint16)(n) & 0x003fu) << _H3A_AFPAX1_PAXV_SHIFT)
#define _H3A_AFPAX1_PAXV_MASK			(_H3A_AFPAX1_PAXV_MK(0x003fu))
#define _H3A_AFPAX1_PAXV_CLR			(~(_H3A_AFPAX1_PAXV_MASK))

#define _H3A_AFPAX1_PAXH_SHIFT		(0)
#define _H3A_AFPAX1_PAXH_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _H3A_AFPAX1_PAXH_MASK			(_H3A_AFPAX1_PAXH_MK(0x00ffu))
#define _H3A_AFPAX1_PAXH_CLR			(~(_H3A_AFPAX1_PAXH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFPAX2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFPAX2_GET()			_REG_GET(_H3A_AFPAX2_ADDR)
#define _H3A_AFPAX2_SET(Val)			_REG_SET(_H3A_AFPAX2_ADDR, Val)
#define _H3A_AFPAX2_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFPAX2_ADDR,AND,OR,INV)
#define _H3A_AFPAX2_FGET(Field)			_FIELD_GET(_H3A_AFPAX2_ADDR, _H3A_AFPAX2_##Field##)
#define _H3A_AFPAX2_FSET(Field, Val)		_FIELD_SET(_H3A_AFPAX2_ADDR, _H3A_AFPAX2_##Field##, Val)
#define _H3A_AFPAX2_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFPAX2_ADDR, _H3A_AFPAX2_##Field##, AND, OR, INV)

#define _H3A_AFPAX2_PAXVC_SHIFT		(8)
#define _H3A_AFPAX2_PAXVC_MK(n)		(((Uint16)(n) & 0x0003u) << _H3A_AFPAX2_PAXVC_SHIFT)
#define _H3A_AFPAX2_PAXVC_MASK			(_H3A_AFPAX2_PAXVC_MK(0x0003u))
#define _H3A_AFPAX2_PAXVC_CLR			(~(_H3A_AFPAX2_PAXVC_MASK))

#define _H3A_AFPAX2_PAXHC_SHIFT		(0)
#define _H3A_AFPAX2_PAXHC_MK(n)		((Uint16)(n) & 0x000fu) 
#define _H3A_AFPAX2_PAXHC_MASK			(_H3A_AFPAX2_PAXHC_MK(0x000fu))
#define _H3A_AFPAX2_PAXHC_CLR			(~(_H3A_AFPAX2_PAXHC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFPAX3 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFPAX3_GET()			_REG_GET(_H3A_AFPAX3_ADDR)
#define _H3A_AFPAX3_SET(Val)			_REG_SET(_H3A_AFPAX3_ADDR, Val)
#define _H3A_AFPAX3_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFPAX3_ADDR,AND,OR,INV)
#define _H3A_AFPAX3_FGET(Field)			_FIELD_GET(_H3A_AFPAX3_ADDR, _H3A_AFPAX3_##Field##)
#define _H3A_AFPAX3_FSET(Field, Val)		_FIELD_SET(_H3A_AFPAX3_ADDR, _H3A_AFPAX3_##Field##, Val)
#define _H3A_AFPAX3_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFPAX3_ADDR, _H3A_AFPAX3_##Field##, AND, OR, INV)

#define _H3A_AFPAX3_PAXSH_SHIFT		(0)
#define _H3A_AFPAX3_PAXSH_MK(n)		((Uint16)(n) & 0x0fffu) 
#define _H3A_AFPAX3_PAXSH_MASK			(_H3A_AFPAX3_PAXSH_MK(0x0fffu))
#define _H3A_AFPAX3_PAXSH_CLR			(~(_H3A_AFPAX3_PAXSH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFPAX4 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFPAX4_GET()			_REG_GET(_H3A_AFPAX4_ADDR)
#define _H3A_AFPAX4_SET(Val)			_REG_SET(_H3A_AFPAX4_ADDR, Val)
#define _H3A_AFPAX4_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFPAX4_ADDR,AND,OR,INV)
#define _H3A_AFPAX4_FGET(Field)			_FIELD_GET(_H3A_AFPAX4_ADDR, _H3A_AFPAX4_##Field##)
#define _H3A_AFPAX4_FSET(Field, Val)		_FIELD_SET(_H3A_AFPAX4_ADDR, _H3A_AFPAX4_##Field##, Val)
#define _H3A_AFPAX4_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFPAX4_ADDR, _H3A_AFPAX4_##Field##, AND, OR, INV)

#define _H3A_AFPAX4_PAXSV_SHIFT		(0)
#define _H3A_AFPAX4_PAXSV_MK(n)		((Uint16)(n) & 0x0fffu) 
#define _H3A_AFPAX4_PAXSV_MASK			(_H3A_AFPAX4_PAXSV_MK(0x0fffu))
#define _H3A_AFPAX4_PAXSV_CLR			(~(_H3A_AFPAX4_PAXSV_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFIIRSH register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFIIRSH_GET()			_REG_GET(_H3A_AFIIRSH_ADDR)
#define _H3A_AFIIRSH_SET(Val)			_REG_SET(_H3A_AFIIRSH_ADDR, Val)
#define _H3A_AFIIRSH_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFIIRSH_ADDR,AND,OR,INV)
#define _H3A_AFIIRSH_FGET(Field)			_FIELD_GET(_H3A_AFIIRSH_ADDR, _H3A_AFIIRSH_##Field##)
#define _H3A_AFIIRSH_FSET(Field, Val)		_FIELD_SET(_H3A_AFIIRSH_ADDR, _H3A_AFIIRSH_##Field##, Val)
#define _H3A_AFIIRSH_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFIIRSH_ADDR, _H3A_AFIIRSH_##Field##, AND, OR, INV)

#define _H3A_AFIIRSH_IIRSH_SHIFT		(0)
#define _H3A_AFIIRSH_IIRSH_MK(n)		((Uint16)(n) & 0x0fffu) 
#define _H3A_AFIIRSH_IIRSH_MASK			(_H3A_AFIIRSH_IIRSH_MK(0x0fffu))
#define _H3A_AFIIRSH_IIRSH_CLR			(~(_H3A_AFIIRSH_IIRSH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFPAX5 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _H3A_AFPAX5_GET()			_REG_GET(_H3A_AFPAX5_ADDR)
#define _H3A_AFPAX5_SET(Val)			_REG_SET(_H3A_AFPAX5_ADDR, Val)
#define _H3A_AFPAX5_AOI(AND,OR,INV)		_REG_AOI(_H3A_AFPAX5_ADDR,AND,OR,INV)
#define _H3A_AFPAX5_FGET(Field)			_FIELD_GET(_H3A_AFPAX5_ADDR, _H3A_AFPAX5_##Field##)
#define _H3A_AFPAX5_FSET(Field, Val)		_FIELD_SET(_H3A_AFPAX5_ADDR, _H3A_AFPAX5_##Field##, Val)
#define _H3A_AFPAX5_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_H3A_AFPAX5_ADDR, _H3A_AFPAX5_##Field##, AND, OR, INV)

#define _H3A_AFPAX5_AFINCV_SHIFT		(8)
#define _H3A_AFPAX5_AFINCV_MK(n)		(((Uint16)(n) & 0x000fu) << _H3A_AFPAX5_AFINCV_SHIFT)
#define _H3A_AFPAX5_AFINCV_MASK			(_H3A_AFPAX5_AFINCV_MK(0x000fu))
#define _H3A_AFPAX5_AFINCV_CLR			(~(_H3A_AFPAX5_AFINCV_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for H3A AFSDRA1 register :
*                                                                                    
*                                                                                    
*