csl_uart0hal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... UART0 - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_uart0hal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for UART0:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for UART0 DTRR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_DTRR0_GET()			_REG_GET(_UART0_DTRR0_ADDR)
#define _UART0_DTRR0_SET(Val)			_REG_SET(_UART0_DTRR0_ADDR, Val)
#define _UART0_DTRR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_DTRR0_ADDR,AND,OR,INV)
#define _UART0_DTRR0_FGET(Field)			_FIELD_GET(_UART0_DTRR0_ADDR, _UART0_DTRR0_##Field##)
#define _UART0_DTRR0_FSET(Field, Val)		_FIELD_SET(_UART0_DTRR0_ADDR, _UART0_DTRR0_##Field##, Val)
#define _UART0_DTRR0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART0_DTRR0_ADDR, _UART0_DTRR0_##Field##, AND, OR, INV)

#define _UART0_DTRR0_RVF_SHIFT		(12)
#define _UART0_DTRR0_RVF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_DTRR0_RVF_SHIFT)
#define _UART0_DTRR0_RVF_MASK			(_UART0_DTRR0_RVF_MK(0x0001u))
#define _UART0_DTRR0_RVF_CLR			(~(_UART0_DTRR0_RVF_MASK))

#define _UART0_DTRR0_BF_SHIFT		(11)
#define _UART0_DTRR0_BF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_DTRR0_BF_SHIFT)
#define _UART0_DTRR0_BF_MASK			(_UART0_DTRR0_BF_MK(0x0001u))
#define _UART0_DTRR0_BF_CLR			(~(_UART0_DTRR0_BF_MASK))

#define _UART0_DTRR0_FE_SHIFT		(10)
#define _UART0_DTRR0_FE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_DTRR0_FE_SHIFT)
#define _UART0_DTRR0_FE_MASK			(_UART0_DTRR0_FE_MK(0x0001u))
#define _UART0_DTRR0_FE_CLR			(~(_UART0_DTRR0_FE_MASK))

#define _UART0_DTRR0_ORF_SHIFT		(9)
#define _UART0_DTRR0_ORF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_DTRR0_ORF_SHIFT)
#define _UART0_DTRR0_ORF_MASK			(_UART0_DTRR0_ORF_MK(0x0001u))
#define _UART0_DTRR0_ORF_CLR			(~(_UART0_DTRR0_ORF_MASK))

#define _UART0_DTRR0_PEF_SHIFT		(8)
#define _UART0_DTRR0_PEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_DTRR0_PEF_SHIFT)
#define _UART0_DTRR0_PEF_MASK			(_UART0_DTRR0_PEF_MK(0x0001u))
#define _UART0_DTRR0_PEF_CLR			(~(_UART0_DTRR0_PEF_MASK))

#define _UART0_DTRR0_DTR_SHIFT		(0)
#define _UART0_DTRR0_DTR_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _UART0_DTRR0_DTR_MASK			(_UART0_DTRR0_DTR_MK(0x00ffu))
#define _UART0_DTRR0_DTR_CLR			(~(_UART0_DTRR0_DTR_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART0 BRSR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_BRSR0_GET()			_REG_GET(_UART0_BRSR0_ADDR)
#define _UART0_BRSR0_SET(Val)			_REG_SET(_UART0_BRSR0_ADDR, Val)
#define _UART0_BRSR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_BRSR0_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for UART0 MSR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_MSR0_GET()			_REG_GET(_UART0_MSR0_ADDR)
#define _UART0_MSR0_SET(Val)			_REG_SET(_UART0_MSR0_ADDR, Val)
#define _UART0_MSR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_MSR0_ADDR,AND,OR,INV)
#define _UART0_MSR0_FGET(Field)			_FIELD_GET(_UART0_MSR0_ADDR, _UART0_MSR0_##Field##)
#define _UART0_MSR0_FSET(Field, Val)		_FIELD_SET(_UART0_MSR0_ADDR, _UART0_MSR0_##Field##, Val)
#define _UART0_MSR0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART0_MSR0_ADDR, _UART0_MSR0_##Field##, AND, OR, INV)

#define _UART0_MSR0_RFTIE_SHIFT		(15)
#define _UART0_MSR0_RFTIE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_MSR0_RFTIE_SHIFT)
#define _UART0_MSR0_RFTIE_MASK			(_UART0_MSR0_RFTIE_MK(0x0001u))
#define _UART0_MSR0_RFTIE_CLR			(~(_UART0_MSR0_RFTIE_MASK))

#define _UART0_MSR0_TFTIE_SHIFT		(14)
#define _UART0_MSR0_TFTIE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_MSR0_TFTIE_SHIFT)
#define _UART0_MSR0_TFTIE_MASK			(_UART0_MSR0_TFTIE_MK(0x0001u))
#define _UART0_MSR0_TFTIE_CLR			(~(_UART0_MSR0_TFTIE_MASK))

#define _UART0_MSR0_REIE_SHIFT		(13)
#define _UART0_MSR0_REIE_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_MSR0_REIE_SHIFT)
#define _UART0_MSR0_REIE_MASK			(_UART0_MSR0_REIE_MK(0x0001u))
#define _UART0_MSR0_REIE_CLR			(~(_UART0_MSR0_REIE_MASK))

#define _UART0_MSR0_TOIC_SHIFT		(10)
#define _UART0_MSR0_TOIC_MK(n)		(((Uint16)(n) & 0x0003u) << _UART0_MSR0_TOIC_SHIFT)
#define _UART0_MSR0_TOIC_MASK			(_UART0_MSR0_TOIC_MK(0x0003u))
#define _UART0_MSR0_TOIC_CLR			(~(_UART0_MSR0_TOIC_MASK))

#define _UART0_MSR0_PEB_SHIFT		(4)
#define _UART0_MSR0_PEB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_MSR0_PEB_SHIFT)
#define _UART0_MSR0_PEB_MASK			(_UART0_MSR0_PEB_MK(0x0001u))
#define _UART0_MSR0_PEB_CLR			(~(_UART0_MSR0_PEB_MASK))

#define _UART0_MSR0_PSB_SHIFT		(3)
#define _UART0_MSR0_PSB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_MSR0_PSB_SHIFT)
#define _UART0_MSR0_PSB_MASK			(_UART0_MSR0_PSB_MK(0x0001u))
#define _UART0_MSR0_PSB_CLR			(~(_UART0_MSR0_PSB_MASK))

#define _UART0_MSR0_SBLS_SHIFT		(2)
#define _UART0_MSR0_SBLS_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_MSR0_SBLS_SHIFT)
#define _UART0_MSR0_SBLS_MASK			(_UART0_MSR0_SBLS_MK(0x0001u))
#define _UART0_MSR0_SBLS_CLR			(~(_UART0_MSR0_SBLS_MASK))

#define _UART0_MSR0_CLS_SHIFT		(0)
#define _UART0_MSR0_CLS_MK(n)		((Uint16)(n) & 0x0001u) 
#define _UART0_MSR0_CLS_MASK			(_UART0_MSR0_CLS_MK(0x0001u))
#define _UART0_MSR0_CLS_CLR			(~(_UART0_MSR0_CLS_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART0 RFCR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_RFCR0_GET()			_REG_GET(_UART0_RFCR0_ADDR)
#define _UART0_RFCR0_SET(Val)			_REG_SET(_UART0_RFCR0_ADDR, Val)
#define _UART0_RFCR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_RFCR0_ADDR,AND,OR,INV)
#define _UART0_RFCR0_FGET(Field)			_FIELD_GET(_UART0_RFCR0_ADDR, _UART0_RFCR0_##Field##)
#define _UART0_RFCR0_FSET(Field, Val)		_FIELD_SET(_UART0_RFCR0_ADDR, _UART0_RFCR0_##Field##, Val)
#define _UART0_RFCR0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART0_RFCR0_ADDR, _UART0_RFCR0_##Field##, AND, OR, INV)

#define _UART0_RFCR0_RFCB_SHIFT		(15)
#define _UART0_RFCR0_RFCB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_RFCR0_RFCB_SHIFT)
#define _UART0_RFCR0_RFCB_MASK			(_UART0_RFCR0_RFCB_MK(0x0001u))
#define _UART0_RFCR0_RFCB_CLR			(~(_UART0_RFCR0_RFCB_MASK))

#define _UART0_RFCR0_RDEF_SHIFT		(14)
#define _UART0_RFCR0_RDEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_RFCR0_RDEF_SHIFT)
#define _UART0_RFCR0_RDEF_MASK			(_UART0_RFCR0_RDEF_MK(0x0001u))
#define _UART0_RFCR0_RDEF_CLR			(~(_UART0_RFCR0_RDEF_MASK))

#define _UART0_RFCR0_RTL_SHIFT		(8)
#define _UART0_RFCR0_RTL_MK(n)		(((Uint16)(n) & 0x0007u) << _UART0_RFCR0_RTL_SHIFT)
#define _UART0_RFCR0_RTL_MASK			(_UART0_RFCR0_RTL_MK(0x0007u))
#define _UART0_RFCR0_RTL_CLR			(~(_UART0_RFCR0_RTL_MASK))

#define _UART0_RFCR0_RWC_SHIFT		(0)
#define _UART0_RFCR0_RWC_MK(n)		((Uint16)(n) & 0x003fu) 
#define _UART0_RFCR0_RWC_MASK			(_UART0_RFCR0_RWC_MK(0x003fu))
#define _UART0_RFCR0_RWC_CLR			(~(_UART0_RFCR0_RWC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART0 TFCR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_TFCR0_GET()			_REG_GET(_UART0_TFCR0_ADDR)
#define _UART0_TFCR0_SET(Val)			_REG_SET(_UART0_TFCR0_ADDR, Val)
#define _UART0_TFCR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_TFCR0_ADDR,AND,OR,INV)
#define _UART0_TFCR0_FGET(Field)			_FIELD_GET(_UART0_TFCR0_ADDR, _UART0_TFCR0_##Field##)
#define _UART0_TFCR0_FSET(Field, Val)		_FIELD_SET(_UART0_TFCR0_ADDR, _UART0_TFCR0_##Field##, Val)
#define _UART0_TFCR0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART0_TFCR0_ADDR, _UART0_TFCR0_##Field##, AND, OR, INV)

#define _UART0_TFCR0_TFCB_SHIFT		(15)
#define _UART0_TFCR0_TFCB_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_TFCR0_TFCB_SHIFT)
#define _UART0_TFCR0_TFCB_MASK			(_UART0_TFCR0_TFCB_MK(0x0001u))
#define _UART0_TFCR0_TFCB_CLR			(~(_UART0_TFCR0_TFCB_MASK))

#define _UART0_TFCR0_TTL_SHIFT		(8)
#define _UART0_TFCR0_TTL_MK(n)		(((Uint16)(n) & 0x0007u) << _UART0_TFCR0_TTL_SHIFT)
#define _UART0_TFCR0_TTL_MASK			(_UART0_TFCR0_TTL_MK(0x0007u))
#define _UART0_TFCR0_TTL_CLR			(~(_UART0_TFCR0_TTL_MASK))

#define _UART0_TFCR0_TWC_SHIFT		(0)
#define _UART0_TFCR0_TWC_MK(n)		((Uint16)(n) & 0x003fu) 
#define _UART0_TFCR0_TWC_MASK			(_UART0_TFCR0_TWC_MK(0x003fu))
#define _UART0_TFCR0_TWC_CLR			(~(_UART0_TFCR0_TWC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART0 LCR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_LCR0_GET()			_REG_GET(_UART0_LCR0_ADDR)
#define _UART0_LCR0_SET(Val)			_REG_SET(_UART0_LCR0_ADDR, Val)
#define _UART0_LCR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_LCR0_ADDR,AND,OR,INV)
#define _UART0_LCR0_FGET(Field)			_FIELD_GET(_UART0_LCR0_ADDR, _UART0_LCR0_##Field##)
#define _UART0_LCR0_FSET(Field, Val)		_FIELD_SET(_UART0_LCR0_ADDR, _UART0_LCR0_##Field##, Val)
#define _UART0_LCR0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART0_LCR0_ADDR, _UART0_LCR0_##Field##, AND, OR, INV)

#define _UART0_LCR0_UTST_SHIFT		(14)
#define _UART0_LCR0_UTST_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_LCR0_UTST_SHIFT)
#define _UART0_LCR0_UTST_MASK			(_UART0_LCR0_UTST_MK(0x0001u))
#define _UART0_LCR0_UTST_CLR			(~(_UART0_LCR0_UTST_MASK))

#define _UART0_LCR0_BOC_SHIFT		(8)
#define _UART0_LCR0_BOC_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_LCR0_BOC_SHIFT)
#define _UART0_LCR0_BOC_MASK			(_UART0_LCR0_BOC_MK(0x0001u))
#define _UART0_LCR0_BOC_CLR			(~(_UART0_LCR0_BOC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for UART0 SR0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _UART0_SR0_GET()			_REG_GET(_UART0_SR0_ADDR)
#define _UART0_SR0_SET(Val)			_REG_SET(_UART0_SR0_ADDR, Val)
#define _UART0_SR0_AOI(AND,OR,INV)		_REG_AOI(_UART0_SR0_ADDR,AND,OR,INV)
#define _UART0_SR0_FGET(Field)			_FIELD_GET(_UART0_SR0_ADDR, _UART0_SR0_##Field##)
#define _UART0_SR0_FSET(Field, Val)		_FIELD_SET(_UART0_SR0_ADDR, _UART0_SR0_##Field##, Val)
#define _UART0_SR0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_UART0_SR0_ADDR, _UART0_SR0_##Field##, AND, OR, INV)

#define _UART0_SR0_RFTI_SHIFT		(11)
#define _UART0_SR0_RFTI_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_SR0_RFTI_SHIFT)
#define _UART0_SR0_RFTI_MASK			(_UART0_SR0_RFTI_MK(0x0001u))
#define _UART0_SR0_RFTI_CLR			(~(_UART0_SR0_RFTI_MASK))

#define _UART0_SR0_TFTI_SHIFT		(10)
#define _UART0_SR0_TFTI_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_SR0_TFTI_SHIFT)
#define _UART0_SR0_TFTI_MASK			(_UART0_SR0_TFTI_MK(0x0001u))
#define _UART0_SR0_TFTI_CLR			(~(_UART0_SR0_TFTI_MASK))

#define _UART0_SR0_RFER_SHIFT		(9)
#define _UART0_SR0_RFER_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_SR0_RFER_SHIFT)
#define _UART0_SR0_RFER_MASK			(_UART0_SR0_RFER_MK(0x0001u))
#define _UART0_SR0_RFER_CLR			(~(_UART0_SR0_RFER_MASK))

#define _UART0_SR0_TOIF_SHIFT		(8)
#define _UART0_SR0_TOIF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_SR0_TOIF_SHIFT)
#define _UART0_SR0_TOIF_MASK			(_UART0_SR0_TOIF_MK(0x0001u))
#define _UART0_SR0_TOIF_CLR			(~(_UART0_SR0_TOIF_MASK))

#define _UART0_SR0_RFNEF_SHIFT		(2)
#define _UART0_SR0_RFNEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_SR0_RFNEF_SHIFT)
#define _UART0_SR0_RFNEF_MASK			(_UART0_SR0_RFNEF_MK(0x0001u))
#define _UART0_SR0_RFNEF_CLR			(~(_UART0_SR0_RFNEF_MASK))

#define _UART0_SR0_TFEF_SHIFT		(1)
#define _UART0_SR0_TFEF_MK(n)		(((Uint16)(n) & 0x0001u) << _UART0_SR0_TFEF_SHIFT)
#define _UART0_SR0_TFEF_MASK			(_UART0_SR0_TFEF_MK(0x0001u))
#define _UART0_SR0_TFEF_CLR			(~(_UART0_SR0_TFEF_MASK))

#define _UART0_SR0_TREF_SHIFT		(0)
#define _UART0_SR0_TREF_MK(n)		((Uint16)(n) & 0x0001u) 
#define _UART0_SR0_TREF_MASK			(_UART0_SR0_TREF_MK(0x0001u))
#define _UART0_SR0_TREF_CLR			(~(_UART0_SR0_TREF_MASK))