csl_mmcsdhal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... MMCSD - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_mmcsdhal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for MMCSD:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for MMCSD MMCCTL register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _MMCSD_MMCCTL_GET()			_REG_GET(_MMCSD_MMCCTL_ADDR)
#define _MMCSD_MMCCTL_SET(Val)			_REG_SET(_MMCSD_MMCCTL_ADDR, Val)
#define _MMCSD_MMCCTL_AOI(AND,OR,INV)		_REG_AOI(_MMCSD_MMCCTL_ADDR,AND,OR,INV)
#define _MMCSD_MMCCTL_FGET(Field)			_FIELD_GET(_MMCSD_MMCCTL_ADDR, _MMCSD_MMCCTL_##Field##)
#define _MMCSD_MMCCTL_FSET(Field, Val)		_FIELD_SET(_MMCSD_MMCCTL_ADDR, _MMCSD_MMCCTL_##Field##, Val)
#define _MMCSD_MMCCTL_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_MMCSD_MMCCTL_ADDR, _MMCSD_MMCCTL_##Field##, AND, OR, INV)

#define _MMCSD_MMCCTL_PERMDX_SHIFT		(10)
#define _MMCSD_MMCCTL_PERMDX_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_PERMDX_SHIFT)
#define _MMCSD_MMCCTL_PERMDX_MASK			(_MMCSD_MMCCTL_PERMDX_MK(0x0001u))
#define _MMCSD_MMCCTL_PERMDX_CLR			(~(_MMCSD_MMCCTL_PERMDX_MASK))

#define _MMCSD_MMCCTL_PERMDR_SHIFT		(9)
#define _MMCSD_MMCCTL_PERMDR_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_PERMDR_SHIFT)
#define _MMCSD_MMCCTL_PERMDR_MASK			(_MMCSD_MMCCTL_PERMDR_MK(0x0001u))
#define _MMCSD_MMCCTL_PERMDR_CLR			(~(_MMCSD_MMCCTL_PERMDR_MASK))

#define _MMCSD_MMCCTL_DATED_SHIFT		(6)
#define _MMCSD_MMCCTL_DATED_MK(n)		(((Uint16)(n) & 0x0003u) << _MMCSD_MMCCTL_DATED_SHIFT)
#define _MMCSD_MMCCTL_DATED_MASK			(_MMCSD_MMCCTL_DATED_MK(0x0003u))
#define _MMCSD_MMCCTL_DATED_CLR			(~(_MMCSD_MMCCTL_DATED_MASK))

#define _MMCSD_MMCCTL_SPIEN_SHIFT		(5)
#define _MMCSD_MMCCTL_SPIEN_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_SPIEN_SHIFT)
#define _MMCSD_MMCCTL_SPIEN_MASK			(_MMCSD_MMCCTL_SPIEN_MK(0x0001u))
#define _MMCSD_MMCCTL_SPIEN_CLR			(~(_MMCSD_MMCCTL_SPIEN_MASK))

#define _MMCSD_MMCCTL_CSEN_SHIFT		(4)
#define _MMCSD_MMCCTL_CSEN_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_CSEN_SHIFT)
#define _MMCSD_MMCCTL_CSEN_MASK			(_MMCSD_MMCCTL_CSEN_MK(0x0001u))
#define _MMCSD_MMCCTL_CSEN_CLR			(~(_MMCSD_MMCCTL_CSEN_MASK))

#define _MMCSD_MMCCTL_SPICRC_SHIFT		(3)
#define _MMCSD_MMCCTL_SPICRC_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_SPICRC_SHIFT)
#define _MMCSD_MMCCTL_SPICRC_MASK			(_MMCSD_MMCCTL_SPICRC_MK(0x0001u))
#define _MMCSD_MMCCTL_SPICRC_CLR			(~(_MMCSD_MMCCTL_SPICRC_MASK))

#define _MMCSD_MMCCTL_WIDTH_SHIFT		(2)
#define _MMCSD_MMCCTL_WIDTH_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_WIDTH_SHIFT)
#define _MMCSD_MMCCTL_WIDTH_MASK			(_MMCSD_MMCCTL_WIDTH_MK(0x0001u))
#define _MMCSD_MMCCTL_WIDTH_CLR			(~(_MMCSD_MMCCTL_WIDTH_MASK))

#define _MMCSD_MMCCTL_CMDRST_SHIFT		(1)
#define _MMCSD_MMCCTL_CMDRST_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCTL_CMDRST_SHIFT)
#define _MMCSD_MMCCTL_CMDRST_MASK			(_MMCSD_MMCCTL_CMDRST_MK(0x0001u))
#define _MMCSD_MMCCTL_CMDRST_CLR			(~(_MMCSD_MMCCTL_CMDRST_MASK))

#define _MMCSD_MMCCTL_DATRST_SHIFT		(0)
#define _MMCSD_MMCCTL_DATRST_MK(n)		((Uint16)(n) & 0x0001u) 
#define _MMCSD_MMCCTL_DATRST_MASK			(_MMCSD_MMCCTL_DATRST_MK(0x0001u))
#define _MMCSD_MMCCTL_DATRST_CLR			(~(_MMCSD_MMCCTL_DATRST_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for MMCSD MMCCLK register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _MMCSD_MMCCLK_GET()			_REG_GET(_MMCSD_MMCCLK_ADDR)
#define _MMCSD_MMCCLK_SET(Val)			_REG_SET(_MMCSD_MMCCLK_ADDR, Val)
#define _MMCSD_MMCCLK_AOI(AND,OR,INV)		_REG_AOI(_MMCSD_MMCCLK_ADDR,AND,OR,INV)
#define _MMCSD_MMCCLK_FGET(Field)			_FIELD_GET(_MMCSD_MMCCLK_ADDR, _MMCSD_MMCCLK_##Field##)
#define _MMCSD_MMCCLK_FSET(Field, Val)		_FIELD_SET(_MMCSD_MMCCLK_ADDR, _MMCSD_MMCCLK_##Field##, Val)
#define _MMCSD_MMCCLK_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_MMCSD_MMCCLK_ADDR, _MMCSD_MMCCLK_##Field##, AND, OR, INV)

#define _MMCSD_MMCCLK_CLEN_SHIFT		(8)
#define _MMCSD_MMCCLK_CLEN_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCCLK_CLEN_SHIFT)
#define _MMCSD_MMCCLK_CLEN_MASK			(_MMCSD_MMCCLK_CLEN_MK(0x0001u))
#define _MMCSD_MMCCLK_CLEN_CLR			(~(_MMCSD_MMCCLK_CLEN_MASK))

#define _MMCSD_MMCCLK_CLKRT_SHIFT		(0)
#define _MMCSD_MMCCLK_CLKRT_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _MMCSD_MMCCLK_CLKRT_MASK			(_MMCSD_MMCCLK_CLKRT_MK(0x00ffu))
#define _MMCSD_MMCCLK_CLKRT_CLR			(~(_MMCSD_MMCCLK_CLKRT_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for MMCSD MMCST0 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _MMCSD_MMCST0_GET()			_REG_GET(_MMCSD_MMCST0_ADDR)
#define _MMCSD_MMCST0_SET(Val)			_REG_SET(_MMCSD_MMCST0_ADDR, Val)
#define _MMCSD_MMCST0_AOI(AND,OR,INV)		_REG_AOI(_MMCSD_MMCST0_ADDR,AND,OR,INV)
#define _MMCSD_MMCST0_FGET(Field)			_FIELD_GET(_MMCSD_MMCST0_ADDR, _MMCSD_MMCST0_##Field##)
#define _MMCSD_MMCST0_FSET(Field, Val)		_FIELD_SET(_MMCSD_MMCST0_ADDR, _MMCSD_MMCST0_##Field##, Val)
#define _MMCSD_MMCST0_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_MMCSD_MMCST0_ADDR, _MMCSD_MMCST0_##Field##, AND, OR, INV)

#define _MMCSD_MMCST0_DATED_SHIFT		(11)
#define _MMCSD_MMCST0_DATED_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_DATED_SHIFT)
#define _MMCSD_MMCST0_DATED_MASK			(_MMCSD_MMCST0_DATED_MK(0x0001u))
#define _MMCSD_MMCST0_DATED_CLR			(~(_MMCSD_MMCST0_DATED_MASK))

#define _MMCSD_MMCST0_DRRDY_SHIFT		(10)
#define _MMCSD_MMCST0_DRRDY_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_DRRDY_SHIFT)
#define _MMCSD_MMCST0_DRRDY_MASK			(_MMCSD_MMCST0_DRRDY_MK(0x0001u))
#define _MMCSD_MMCST0_DRRDY_CLR			(~(_MMCSD_MMCST0_DRRDY_MASK))

#define _MMCSD_MMCST0_DXRDY_SHIFT		(9)
#define _MMCSD_MMCST0_DXRDY_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_DXRDY_SHIFT)
#define _MMCSD_MMCST0_DXRDY_MASK			(_MMCSD_MMCST0_DXRDY_MK(0x0001u))
#define _MMCSD_MMCST0_DXRDY_CLR			(~(_MMCSD_MMCST0_DXRDY_MASK))

#define _MMCSD_MMCST0_SPIERR_SHIFT		(8)
#define _MMCSD_MMCST0_SPIERR_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_SPIERR_SHIFT)
#define _MMCSD_MMCST0_SPIERR_MASK			(_MMCSD_MMCST0_SPIERR_MK(0x0001u))
#define _MMCSD_MMCST0_SPIERR_CLR			(~(_MMCSD_MMCST0_SPIERR_MASK))

#define _MMCSD_MMCST0_CRCRS_SHIFT		(7)
#define _MMCSD_MMCST0_CRCRS_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_CRCRS_SHIFT)
#define _MMCSD_MMCST0_CRCRS_MASK			(_MMCSD_MMCST0_CRCRS_MK(0x0001u))
#define _MMCSD_MMCST0_CRCRS_CLR			(~(_MMCSD_MMCST0_CRCRS_MASK))

#define _MMCSD_MMCST0_CRCRD_SHIFT		(6)
#define _MMCSD_MMCST0_CRCRD_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_CRCRD_SHIFT)
#define _MMCSD_MMCST0_CRCRD_MASK			(_MMCSD_MMCST0_CRCRD_MK(0x0001u))
#define _MMCSD_MMCST0_CRCRD_CLR			(~(_MMCSD_MMCST0_CRCRD_MASK))

#define _MMCSD_MMCST0_CRCWR_SHIFT		(5)
#define _MMCSD_MMCST0_CRCWR_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_CRCWR_SHIFT)
#define _MMCSD_MMCST0_CRCWR_MASK			(_MMCSD_MMCST0_CRCWR_MK(0x0001u))
#define _MMCSD_MMCST0_CRCWR_CLR			(~(_MMCSD_MMCST0_CRCWR_MASK))

#define _MMCSD_MMCST0_TOUTRS_SHIFT		(4)
#define _MMCSD_MMCST0_TOUTRS_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_TOUTRS_SHIFT)
#define _MMCSD_MMCST0_TOUTRS_MASK			(_MMCSD_MMCST0_TOUTRS_MK(0x0001u))
#define _MMCSD_MMCST0_TOUTRS_CLR			(~(_MMCSD_MMCST0_TOUTRS_MASK))

#define _MMCSD_MMCST0_TOUTRD_SHIFT		(3)
#define _MMCSD_MMCST0_TOUTRD_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_TOUTRD_SHIFT)
#define _MMCSD_MMCST0_TOUTRD_MASK			(_MMCSD_MMCST0_TOUTRD_MK(0x0001u))
#define _MMCSD_MMCST0_TOUTRD_CLR			(~(_MMCSD_MMCST0_TOUTRD_MASK))

#define _MMCSD_MMCST0_RSPDNE_SHIFT		(2)
#define _MMCSD_MMCST0_RSPDNE_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_RSPDNE_SHIFT)
#define _MMCSD_MMCST0_RSPDNE_MASK			(_MMCSD_MMCST0_RSPDNE_MK(0x0001u))
#define _MMCSD_MMCST0_RSPDNE_CLR			(~(_MMCSD_MMCST0_RSPDNE_MASK))

#define _MMCSD_MMCST0_BSYDNE_SHIFT		(1)
#define _MMCSD_MMCST0_BSYDNE_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST0_BSYDNE_SHIFT)
#define _MMCSD_MMCST0_BSYDNE_MASK			(_MMCSD_MMCST0_BSYDNE_MK(0x0001u))
#define _MMCSD_MMCST0_BSYDNE_CLR			(~(_MMCSD_MMCST0_BSYDNE_MASK))

#define _MMCSD_MMCST0_DATDNE_SHIFT		(0)
#define _MMCSD_MMCST0_DATDNE_MK(n)		((Uint16)(n) & 0x0001u) 
#define _MMCSD_MMCST0_DATDNE_MASK			(_MMCSD_MMCST0_DATDNE_MK(0x0001u))
#define _MMCSD_MMCST0_DATDNE_CLR			(~(_MMCSD_MMCST0_DATDNE_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for MMCSD MMCST1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _MMCSD_MMCST1_GET()			_REG_GET(_MMCSD_MMCST1_ADDR)
#define _MMCSD_MMCST1_SET(Val)			_REG_SET(_MMCSD_MMCST1_ADDR, Val)
#define _MMCSD_MMCST1_AOI(AND,OR,INV)		_REG_AOI(_MMCSD_MMCST1_ADDR,AND,OR,INV)
#define _MMCSD_MMCST1_FGET(Field)			_FIELD_GET(_MMCSD_MMCST1_ADDR, _MMCSD_MMCST1_##Field##)
#define _MMCSD_MMCST1_FSET(Field, Val)		_FIELD_SET(_MMCSD_MMCST1_ADDR, _MMCSD_MMCST1_##Field##, Val)
#define _MMCSD_MMCST1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_MMCSD_MMCST1_ADDR, _MMCSD_MMCST1_##Field##, AND, OR, INV)

#define _MMCSD_MMCST1_DAT3ST_SHIFT		(4)
#define _MMCSD_MMCST1_DAT3ST_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST1_DAT3ST_SHIFT)
#define _MMCSD_MMCST1_DAT3ST_MASK			(_MMCSD_MMCST1_DAT3ST_MK(0x0001u))
#define _MMCSD_MMCST1_DAT3ST_CLR			(~(_MMCSD_MMCST1_DAT3ST_MASK))

#define _MMCSD_MMCST1_DRFUL_SHIFT		(3)
#define _MMCSD_MMCST1_DRFUL_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST1_DRFUL_SHIFT)
#define _MMCSD_MMCST1_DRFUL_MASK			(_MMCSD_MMCST1_DRFUL_MK(0x0001u))
#define _MMCSD_MMCST1_DRFUL_CLR			(~(_MMCSD_MMCST1_DRFUL_MASK))

#define _MMCSD_MMCST1_DXEMP_SHIFT		(2)
#define _MMCSD_MMCST1_DXEMP_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST1_DXEMP_SHIFT)
#define _MMCSD_MMCST1_DXEMP_MASK			(_MMCSD_MMCST1_DXEMP_MK(0x0001u))
#define _MMCSD_MMCST1_DXEMP_CLR			(~(_MMCSD_MMCST1_DXEMP_MASK))

#define _MMCSD_MMCST1_CLKSTP_SHIFT		(1)
#define _MMCSD_MMCST1_CLKSTP_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCST1_CLKSTP_SHIFT)
#define _MMCSD_MMCST1_CLKSTP_MASK			(_MMCSD_MMCST1_CLKSTP_MK(0x0001u))
#define _MMCSD_MMCST1_CLKSTP_CLR			(~(_MMCSD_MMCST1_CLKSTP_MASK))

#define _MMCSD_MMCST1_BUSY_SHIFT		(0)
#define _MMCSD_MMCST1_BUSY_MK(n)		((Uint16)(n) & 0x0001u) 
#define _MMCSD_MMCST1_BUSY_MASK			(_MMCSD_MMCST1_BUSY_MK(0x0001u))
#define _MMCSD_MMCST1_BUSY_CLR			(~(_MMCSD_MMCST1_BUSY_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for MMCSD MMCIE register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _MMCSD_MMCIE_GET()			_REG_GET(_MMCSD_MMCIE_ADDR)
#define _MMCSD_MMCIE_SET(Val)			_REG_SET(_MMCSD_MMCIE_ADDR, Val)
#define _MMCSD_MMCIE_AOI(AND,OR,INV)		_REG_AOI(_MMCSD_MMCIE_ADDR,AND,OR,INV)
#define _MMCSD_MMCIE_FGET(Field)			_FIELD_GET(_MMCSD_MMCIE_ADDR, _MMCSD_MMCIE_##Field##)
#define _MMCSD_MMCIE_FSET(Field, Val)		_FIELD_SET(_MMCSD_MMCIE_ADDR, _MMCSD_MMCIE_##Field##, Val)
#define _MMCSD_MMCIE_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_MMCSD_MMCIE_ADDR, _MMCSD_MMCIE_##Field##, AND, OR, INV)

#define _MMCSD_MMCIE_EDATED_SHIFT		(11)
#define _MMCSD_MMCIE_EDATED_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCIE_EDATED_SHIFT)
#define _MMCSD_MMCIE_EDATED_MASK			(_MMCSD_MMCIE_EDATED_MK(0x0001u))
#define _MMCSD_MMCIE_EDATED_CLR			(~(_MMCSD_MMCIE_EDATED_MASK))

#define _MMCSD_MMCIE_EDRRDY_SHIFT		(10)
#define _MMCSD_MMCIE_EDRRDY_MK(n)		(((Uint16)(n) & 0x0001u) << _MMCSD_MMCIE_EDRRDY_SHIFT)