armcsl_addr_270.h

dm270 source code

#define _SDRC_SDPRTY6_ADDR             ( 0x000309B4 ) /* reg address: SDRAM Priority Select #6 (ARM CPU)            */
#define _SDRC_SDPRTY7_ADDR             ( 0x000309B6 ) /* reg address: SDRAM Priority Select #7 (EMIF #1)            */
#define _SDRC_SDPRTY8_ADDR             ( 0x000309B8 ) /* reg address: SDRAM Priority Select #8 (EMIF #2)            */
#define _SDRC_SDPRTY9_ADDR             ( 0x000309BA ) /* reg address: SDRAM Priority Select #9 (Image Buffer - DSP) */
#define _SDRC_SDPRTY10_ADDR            ( 0x000309BC ) /* reg address: SDRAM Priority Select #10 (Refresh)           */
#define _SDRC_PRTYON_ADDR              ( 0x000309BE ) /* reg address: SDRAM Priority On Register                    */
#define _SDRC_SDRCTEST_ADDR            ( 0x000309C0 ) /* reg address: SDRAM Test                                    */

/*------------------------------------------------------------*/
/*----- Constant definitions for EMIF register addresses -----*/
#define _EMIF_BASE_REG_ADDR            ( 0x00030A00 ) /* reg address: EMIF module base address                      */
#define _EMIF_CS0CTRL1_ADDR            ( 0x00030A00 ) /* reg address: CS0 Control Register #1                                 */
#define _EMIF_CS0CTRL2_ADDR            ( 0x00030A02 ) /* reg address: CS0 Control Register #2                                 */
#define _EMIF_CS1CTRL1A_ADDR           ( 0x00030A04 ) /* reg address: CS1 Control Register #1A                                */
#define _EMIF_CS1CTRL1B_ADDR           ( 0x00030A06 ) /* reg address: CS1 Control Register #1B                                */
#define _EMIF_CS1CTRL2_ADDR            ( 0x00030A08 ) /* reg address: CS1 Control Register #2                                 */
#define _EMIF_CS2CTRL1_ADDR            ( 0x00030A0A ) /* reg address: CS2 Control Register #1                                 */
#define _EMIF_CS2CTRL2_ADDR            ( 0x00030A0C ) /* reg address: CS2 Control Register #2                                                               */
#define _EMIF_CS3CTRL1_ADDR            ( 0x00030A0E ) /* reg address: CS3 Control Register #1                                 */
#define _EMIF_CS3CTRL2_ADDR            ( 0x00030A10 ) /* reg address: CS3 Control Register #2                                 */
#define _EMIF_CS4CTRL1_ADDR            ( 0x00030A12 ) /* reg address: CS4 Control Register #1                                 */
#define _EMIF_CS4CTRL2_ADDR            ( 0x00030A14 ) /* reg address: CS4 Control Register #2                                 */
#define _EMIF_BUSCTRL_ADDR             ( 0x00030A16 ) /* reg address: Bus Control Register                                    */
#define _EMIF_BUSRLS_ADDR              ( 0x00030A18 ) /* reg address: Bus Release Control Register                            */
#define _EMIF_CFCTRL1_ADDR             ( 0x00030A1A ) /* reg address: CFC Control Register #1                                 */
#define _EMIF_CFCTRL2_ADDR             ( 0x00030A1C ) /* reg address: CFC Control Register #2                                 */
#define _EMIF_SMCTRL_ADDR              ( 0x00030A1E ) /* reg address: SmartMedia Control Register                             */
#define _EMIF_BUSINTEN_ADDR            ( 0x00030A20 ) /* reg address: Bus Interrupt Enable Register                           */
#define _EMIF_RSV0_ADDR                ( 0x00030A22 ) /* reg address: Reserved. Do not use                                    */
#define _EMIF_BUSSTS_ADDR              ( 0x00030A24 ) /* reg address: Bus Status Register                                     */
#define _EMIF_BUSWAITMD_ADDR           ( 0x00030A26 ) /* reg address: Bus Wait Mode Register                                  */
#define _EMIF_ECC1CP_ADDR              ( 0x00030A28 ) /* reg address: ECC Area 1 CP Register                                  */
#define _EMIF_ECC1LP_ADDR              ( 0x00030A2A ) /* reg address: ECC Area 1 LP Register                                  */
#define _EMIF_ECC2CP_ADDR              ( 0x00030A2C ) /* reg address: ECC Area 2 CP Register                                  */
#define _EMIF_ECC2LP_ADDR              ( 0x00030A2E ) /* reg address: ECC Area 2 LP Register                                  */
#define _EMIF_ECCCLR_ADDR              ( 0x00030A30 ) /* reg address: ECC Clear Register                                      */
#define _EMIF_PAGESZ_ADDR              ( 0x00030A32 ) /* reg address: SmartMedia Page Size Register                           */
#define _EMIF_IMGDSPDEST_ADDR          ( 0x00030A34 ) /* reg address: Imgae Buffer/DSP(HPIB) Device Select Register           */
#define _EMIF_PRIOCTL_ADDR             ( 0x00030A36 ) /* reg address: Priority Control Register                               */
#define _EMIF_SOURCEADDH_ADDR          ( 0x00030A38 ) /* reg address: DMA Source Address High Register                        */
#define _EMIF_SOURCEADDL_ADDR          ( 0x00030A3A ) /* reg address: DMA Source Address Low Register                         */
#define _EMIF_DESTADDH_ADDR            ( 0x00030A3C ) /* reg address: DMA Destination Address High Register                   */
#define _EMIF_DESTADDL_ADDR            ( 0x00030A3E ) /* reg address: DMA Destination Address Low Register                    */
#define _EMIF_DMASIZE_ADDR             ( 0x00030A40 ) /* reg address: DMA Transfer Size Register                              */
#define _EMIF_DMADEVSEL_ADDR           ( 0x00030A42 ) /* reg address: DMA Device Select Register                              */
#define _EMIF_DMACTL_ADDR              ( 0x00030A44 ) /* reg address: DMA Control Register                                    */
#define _EMIF_IMGDSPADDH_ADDR          ( 0x00030A46 ) /* reg address: Image Buffer/DSP(HPIB) Destination Address High         */
#define _EMIF_IMGDSPADDL_ADDR          ( 0x00030A48 ) /* reg address: Image Buffer/DSP(HPIB) Destination Address Low          */
#define _EMIF_DPSTR0_ADDR              ( 0x00030A4A ) /* reg address: EMIF Region 0 End Address                               */
#define _EMIF_DPSTR1_ADDR              ( 0x00030A4C ) /* reg address: SDRAM Region End Address                                */
#define _EMIF_DPSTR2_ADDR              ( 0x00030A4E ) /* reg address: EMIF Region 1 End Address                               */
#define _EMIF_DPSTR3_ADDR              ( 0x00030A50 ) /* reg address: EMIF Region 2 End Address                               */
#define _EMIF_DPSTR4_ADDR              ( 0x00030A52 ) /* reg address: EMIF Region 3 End Address                               */
#define _EMIF_DPSTR5_ADDR              ( 0x00030A54 ) /* reg address: EMIF Region 4 End Address                               */
#define _EMIF_TEST_ADDR                ( 0x00030A56 ) /* reg address: Test Register. Do not use                               */

/*-----------------------------------------------------------*/
/*----- Constant definitions for USB register addresses -----*/
#define _USB_BASE_REG_ADDR            ( 0x00030A80 ) /* reg address: USB module base address                       */
#define _USB_EP0OAD_ADDR              ( 0x00030A80 ) /* reg address: Endpoint 0 OUT Buffer Address                 */
#define _USB_EP0OSZ_ADDR              ( 0x00030A82 ) /* reg address: Endpoint 0 OUT Buffer Size                    */
#define _USB_EP0OCTL_ADDR             ( 0x00030A84 ) /* reg address: Endpoint 0 OUT Control                        */
#define _USB_EP0OIRQSZ_ADDR           ( 0x00030A86 ) /* reg address: Endpoint 0 OUT Interrupt Size Threshold       */
#define _USB_EP0ORDT_ADDR             ( 0x00030A8A ) /* reg address: Endpoint 0 OUT Read Data Port                 */
#define _USB_EP0OREST_ADDR            ( 0x00030A8C ) /* reg address: Endpoint 0 OUT Data Remaining                 */
#define _USB_EP0OST_ADDR              ( 0x00030A8E ) /* reg address: Endpoint 0 OUT Status                         */
#define _USB_EP0IAD_ADDR              ( 0x00030A90 ) /* reg address: Endpoint 0 IN Buffer Address                  */
#define _USB_EP0ISZ_ADDR              ( 0x00030A92 ) /* reg address: Endpoint 0 IN Buffer Size                     */
#define _USB_EP0ICTL_ADDR             ( 0x00030A94 ) /* reg address: Endpoint 0 IN Control                         */
#define _USB_EP0IIRQSZ_ADDR           ( 0x00030A96 ) /* reg address: Endpoint 0 IN Interrupt Size                  */
#define _USB_EP0IWDT_ADDR             ( 0x00030A98 ) /* reg address: Endpoint 0 IN Write Data Port                 */
#define _USB_EP0IREST_ADDR            ( 0x00030A9C ) /* reg address: Endpoint 0 IN Remainder                       */
#define _USB_EP0IST_ADDR              ( 0x00030A9E ) /* reg address: Endpoint 0 IN Status                          */
#define _USB_EP1OAD_ADDR              ( 0x00030AA0 ) /* reg address: Endpoint 1 OUT Buffer Address                 */
#define _USB_EP1OSZ_ADDR              ( 0x00030AA2 ) /* reg address: Endpoint 1 OUT Buffer Size                    */
#define _USB_EP1OCTL_ADDR             ( 0x00030AA4 ) /* reg address: Endpoint 1 OUT Control                        */
#define _USB_EP1OIRQSZ_ADDR           ( 0x00030AA6 ) /* reg address: Endpoint 1 OUT Interrupt Size Threshold       */
#define _USB_EP1ORDT_ADDR             ( 0x00030AAA ) /* reg address: Endpoint 1 OUT Read Data Port                 */
#define _USB_EP1OREST_ADDR            ( 0x00030AAC ) /* reg address: Endpoint 1 OUT Data Remaining                 */
#define _USB_EP1OST_ADDR              ( 0x00030AAE ) /* reg address: Endpoint 1 OUT Status                         */
#define _USB_EP1IAD_ADDR              ( 0x00030AB0 ) /* reg address: Endpoint 1 IN Buffer Address                  */
#define _USB_EP1ISZ_ADDR              ( 0x00030AB2 ) /* reg address: Endpoint 1 IN Buffer Size                     */
#define _USB_EP1ICTL_ADDR             ( 0x00030AB4 ) /* reg address: Endpoint 1 IN Control                         */
#define _USB_EP1IIRQSZ_ADDR           ( 0x00030AB6 ) /* reg address: Endpoint 1 IN INterrupt Size                  */
#define _USB_EP1IWDT_ADDR             ( 0x00030AB8 ) /* reg address: Endpoint 1 IN Write Data Port                 */
#define _USB_EP1IREST_ADDR            ( 0x00030ABC ) /* reg address: Endpoint 1 IN Remainder                       */
#define _USB_EP1IST_ADDR              ( 0x00030ABE ) /* reg address: Endpoint 1 IN Status                          */
#define _USB_EP2IAD_ADDR              ( 0x00030AC0 ) /* reg address: Endpoint 2 IN Buffer Address                  */
#define _USB_EP2ISZ_ADDR              ( 0x00030AC2 ) /* reg address: Endpoint 2 IN Buffer Size                     */
#define _USB_EP2ICTL_ADDR             ( 0x00030AC4 ) /* reg address: Endpoint 2 IN Control                         */
#define _USB_EP2IIRQSZ_ADDR           ( 0x00030AC6 ) /* reg address: Endpoint 2 IN Interrupt Size Threshold        */
#define _USB_EP2IWDT_ADDR             ( 0x00030AC8 ) /* reg address: Endpoint 2 IN Read Data Port                  */
#define _USB_EP2IREST_ADDR            ( 0x00030ACC ) /* reg address: Endpoint 2 IN Data Remaining                  */
#define _USB_EP2IST_ADDR              ( 0x00030ACE ) /* reg address: Endpoint 2 IN Status                          */
#define _USB_EP3IAD_ADDR              ( 0x00030AD0 ) /* reg address: Endpoint 3 IN Buffer Address                  */
#define _USB_EP3ISZ_ADDR              ( 0x00030AD2 ) /* reg address: Endpoint 3 IN Buffer Size                     */
#define _USB_EP3ICTL_ADDR             ( 0x00030AD4 ) /* reg address: Endpoint 3 IN Control                         */
#define _USB_EP3IIRQSZ_ADDR           ( 0x00030AD6 ) /* reg address: Endpoint 3 IN INterrupt Size                  */
#define _USB_EP3IWDT_ADDR             ( 0x00030AD8 ) /* reg address: Endpoint 3 IN Write Data Port                 */
#define _USB_EP3IREST_ADDR            ( 0x00030ADC ) /* reg address: Endpoint 3 IN Remainder                       */
#define _USB_EP3IST_ADDR              ( 0x00030ADE ) /* reg address: Endpoint 3 IN Status                          */
#define _USB_USBRST_ADDR              ( 0x00030B00 ) /* reg address: USB Reset                                     */
#define _USB_USBRSM_ADDR              ( 0x00030B02 ) /* reg address: USB Resume                                    */
#define _USB_USBINTMSK_ADDR           ( 0x00030B04 ) /* reg address: USB Interrupt Mask                            */
#define _USB_USBCFG_ADDR              ( 0x00030B06 ) /* reg address: USB Configuration                             */
#define _USB_USBST_ADDR               ( 0x00030B08 ) /* reg address: USB Status                                    */
#define _USB_USBINTST_ADDR            ( 0x00030B0A ) /* reg address: USB Interrupt Status/Reset                    */
#define _USB_USBFRM_ADDR              ( 0x00030B0C ) /* reg address: USB Frame                                     */
#define _USB_USBALT_ADDR              ( 0x00030B0E ) /* reg address: USB Alternate                                 */
#define _USB_USBCTL_ADDR              ( 0x00030B10 ) /* reg address: USB Control                                   */
#define _USB_DMAAD0_ADDR              ( 0x00030B12 ) /* reg address: DMA Address 0 (low order bits)                */
#define _USB_DMAAD1_ADDR              ( 0x00030B14 ) /* reg address: DMA Address 1 (high order bits)               */
#define _USB_DMASZ_ADDR               ( 0x00030B16 ) /* reg address: DMA Size                                      */
#define _USB_DMACTL_ADDR              ( 0x00030B18 ) /* reg address: DMA Control                                   */
#define _USB_DMATRG_ADDR              ( 0x00030B1A ) /* reg address: DMA Trigger                                   */
#define _USB_DMAREST_ADDR             ( 0x00030B1C ) /* reg address: DMA Packets Remaining                         */
#define _USB_DMAST_ADDR               ( 0x00030B1E ) /* reg address: DMA Short Packet Received Status              */

/*-----------------------------------------------------------*/
/*----- Constant definitions for H3A register addresses -----*/
#define _H3A_BASE_REG_ADDR            ( 0x00030B80 ) /* reg address: H3A module base address                       */
#define _H3A_H3ACTRL_ADDR             (