📄 armcsl_addr_270.h
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#define _PREV_MTXOFST0_ADDR ( 0x000307B2 ) /* reg address: R_offset register */
#define _PREV_MTXOFST1_ADDR ( 0x000307B4 ) /* reg address: G_offset register */
#define _PREV_MTXOFST2_ADDR ( 0x000307B6 ) /* reg address: B_offset register */
#define _PREV_GAMTSBYP_ADDR ( 0x000307B8 ) /* reg address: GAMMA table bypass register */
#define _PREV_CSC0_ADDR ( 0x000307BA ) /* reg address: Color Space Conversion Coefficient register #0 */
#define _PREV_CSC1_ADDR ( 0x000307BC ) /* reg address: Color Space Conversion Coefficient register #1 */
#define _PREV_CSC2_ADDR ( 0x000307BE ) /* reg address: Color Space Conversion Coefficient register #2 */
#define _PREV_CSC3_ADDR ( 0x000307C0 ) /* reg address: Color Space Conversion Coefficient register #3 */
#define _PREV_CSC4_ADDR ( 0x000307C2 ) /* reg address: Color Space Conversion Coefficient register #4 */
#define _PREV_YOFST_ADDR ( 0x000307C4 ) /* reg address: Y offset register */
#define _PREV_COFST_ADDR ( 0x000307C6 ) /* reg address: Cb and Cr offset register */
#define _PREV_CNTBRT_ADDR ( 0x000307C8 ) /* reg address: Contrast and brightness adjustment register */
#define _PREV_CSUP0_ADDR ( 0x000307CA ) /* reg address: Chroma Suppression Register #0 */
#define _PREV_CSUP1_ADDR ( 0x000307CC ) /* reg address: Chroma Suppression Register #1 */
#define _PREV_SETUPY_ADDR ( 0x000307CE ) /* reg address: Y max and min setup register */
#define _PREV_SETUPC_ADDR ( 0x000307D0 ) /* reg address: Cb and Cr max and min setup register */
/*------------------------------------------------------------*/
/*----- Constant definitions for VENC register addresses -----*/
#define _VENC_BASE_REG_ADDR ( 0x00030800 ) /* reg address: VENC module base address */
#define _VENC_VID01_ADDR ( 0x00030800 ) /* reg address: Video Mode Setup #1 */
#define _VENC_VID02_ADDR ( 0x00030802 ) /* reg address: Video Mode Setup #2 */
#define _VENC_DLCD1_ADDR ( 0x00030804 ) /* reg address: Digital LCD Mode Setup #1 */
#define _VENC_DLCD2_ADDR ( 0x00030806 ) /* reg address: Digital LCD Mode Setup #2 */
#define _VENC_DCLKPTN0E_ADDR ( 0x00030808 ) /* reg address: DCLK Pattern Register #0 - EVEN Line */
#define _VENC_DCLKPTN1E_ADDR ( 0x0003080A ) /* reg address: DCLK Pattern Register #1 - EVEN Line */
#define _VENC_DCLKPTN2E_ADDR ( 0x0003080C ) /* reg address: DCLK Pattern Register #2 - EVEN Line */
#define _VENC_DCLKPTN3E_ADDR ( 0x0003080E ) /* reg address: DCLK Pattern Register #3 - EVEN Line */
#define _VENC_DCLKPTN0O_ADDR ( 0x00030810 ) /* reg address: DCLK Pattern Register #0 - ODD Line */
#define _VENC_DCLKPTN1O_ADDR ( 0x00030812 ) /* reg address: DCLK Pattern Register #1 - ODD Line */
#define _VENC_DCLKPTN2O_ADDR ( 0x00030814 ) /* reg address: DCLK Pattern Register #2 - ODD Line */
#define _VENC_DCLKPTN3O_ADDR ( 0x00030816 ) /* reg address: DCLK Pattern Register #3 - ODD Line */
#define _VENC_DCLKSTPHE_ADDR ( 0x00030818 ) /* reg address: DCLK Enable Start Position in Horizontal - Even Line */
#define _VENC_DCLKSTPHO_ADDR ( 0x0003081A ) /* reg address: DCLK Enable Start Position in Horizontal - Odd line */
#define _VENC_DCLKVLDH_ADDR ( 0x0003081C ) /* reg address: DCLK Valid Area in Horizontal */
#define _VENC_DCLKSTPV_ADDR ( 0x0003081E ) /* reg address: DCLK Enable Start Position in Vertical */
#define _VENC_DCLKVLDV_ADDR ( 0x00030820 ) /* reg address: DCLK Valid Area in Vertical */
#define _VENC_HVPWIDTH_ADDR ( 0x00030822 ) /* reg address: Horizontal and Vertical Sync Pulse Width Control */
#define _VENC_HINTERVL_ADDR ( 0x00030824 ) /* reg address: Horizontal Sync Interval Control */
#define _VENC_HSTART_ADDR ( 0x00030826 ) /* reg address: Horizontal Start Position Control */
#define _VENC_HVALID_ADDR ( 0x00030828 ) /* reg address: Horizontal Valid Area Control */
#define _VENC_VINTERVL_ADDR ( 0x0003082A ) /* reg address: Vertical Sync Interval Control */
#define _VENC_VSTART_ADDR ( 0x0003082C ) /* reg address: Vertical Start Position Control */
#define _VENC_VVALID_ADDR ( 0x0003082E ) /* reg address: Vertical Valid Area Control */
#define _VENC_HDELAY_ADDR ( 0x00030830 ) /* reg address: Horizontal Sync Delay */
#define _VENC_VDELAY_ADDR ( 0x00030832 ) /* reg address: Vertical Sync Delay */
#define _VENC_CULLLINE_ADDR ( 0x00030834 ) /* reg address: Line Culling Control */
#define _VENC_PWMCTRL_ADDR ( 0x00030836 ) /* reg address: PWM Control */
#define _VENC_PWMCNT_ADDR ( 0x00030838 ) /* reg address: PWM Count */
#define _VENC_RGBLEVEL_ADDR ( 0x0003083A ) /* reg address: RGB Level Control */
#define _VENC_ATR0_ADDR ( 0x0003083C ) /* reg address: Video Attribute Data #0 */
#define _VENC_ATR1_ADDR ( 0x0003083E ) /* reg address: Video Attribute Data #1 */
#define _VENC_ATR2_ADDR ( 0x00030840 ) /* reg address: Video Attribute Data #2 */
#define _VENC_REC656_ADDR ( 0x00030842 ) /* reg address: CCIR 656 Mode Setup */
#define _VENC_EPSON_LCD_ADDR ( 0x00030844 ) /* reg address: EPSON LCD Control */
#define _VENC_GCPDATA_ADDR ( 0x00030846 ) /* reg address: GCPDATA */
#define _VENC_CASIO_ADDR ( 0x00030848 ) /* reg address: CASIO LCD Control */
#define _VENC_DOUTCTL_ADDR ( 0x0003084A ) /* reg address: Digital Output Control */
#define _VENC_SGHSYNP_ADDR ( 0x0003084C ) /* reg address: Sync Period */
/*------------------------------------------------------------*/
/*----- Constant definitions for CLKC register addresses -----*/
#define _CLKC_BASE_REG_ADDR ( 0x00030880 ) /* reg address: CLKC module base address */
#define _CLKC_PLLA_ADDR ( 0x00030880 ) /* reg address: PLLA Configuration */
#define _CLKC_PLLB_ADDR ( 0x00030882 ) /* reg address: PLLB Configuration */
#define _CLKC_CLKC_ADDR ( 0x00030884 ) /* reg address: Input clock Source Selection */
#define _CLKC_SEL_ADDR ( 0x00030886 ) /* reg address: Input clock Source Selection */
#define _CLKC_DIV_ADDR ( 0x00030888 ) /* reg address: PLL Clock Divisor Settings */
#define _CLKC_BYP_ADDR ( 0x0003088A ) /* reg address: PLL Bypass Configuration */
#define _CLKC_MMCCLK_ADDR ( 0x0003088C ) /* reg address: MMC Clock Divisor Settings */
#define _CLKC_CTEST_ADDR ( 0x0003088E ) /* reg address: Test Register. Do not use. */
#define _CLKC_MOD0_ADDR ( 0x00030890 ) /* reg address: Module Clock Enables #0 */
#define _CLKC_MOD1_ADDR ( 0x00030892 ) /* reg address: Module Clock Enables #1 */
#define _CLKC_MOD2_ADDR ( 0x00030894 ) /* reg address: Module Clock Enables #2 */
#define _CLKC_LPCTL0_ADDR ( 0x00030896 ) /* reg address: Low Power Control #0 */
#define _CLKC_LPCTL1_ADDR ( 0x00030898 ) /* reg address: Low Power Control #1 */
#define _CLKC_OSEL_ADDR ( 0x0003089A ) /* reg address: Output Clock Selector */
#define _CLKC_O0DIV_ADDR ( 0x0003089C ) /* reg address: Output Clock #0 Divider */
#define _CLKC_O1DIV_ADDR ( 0x0003089E ) /* reg address: Output Clock #1 Divider */
#define _CLKC_O2DIV_ADDR ( 0x000308A0 ) /* reg address: Output Clock #2 Divider */
#define _CLKC_PWM0C_ADDR ( 0x000308A2 ) /* reg address: PWM #0 Cycle Count */
#define _CLKC_PWM0H_ADDR ( 0x000308A4 ) /* reg address: PWM #0 High Period */
#define _CLKC_PWM1C_ADDR ( 0x000308A6 ) /* reg address: PWM #1 Cycle Count */
#define _CLKC_PWM1H_ADDR ( 0x000308A8 ) /* reg address: PWM #1 High Period */
/*------------------------------------------------------------*/
/*----- Constant definitions for BUSC register addresses -----*/
#define _BUSC_BASE_REG_ADDR ( 0x00030900 ) /* reg address: BUSC module base address */
#define _BUSC_ECR_ADDR ( 0x00030900 ) /* reg address: Endian Conversion Register */
#define _BUSC_EBYTER_ADDR ( 0x00030902 ) /* reg address: Endian Byte Reverse Register */
#define _BUSC_EBITR_ADDR ( 0x00030904 ) /* reg address: Endian Bit Reverse Register */
#define _BUSC_REVR_ADDR ( 0x00030906 ) /* reg address: Device Revision Register */
/*------------------------------------------------------------*/
/*----- Constant definitions for SDRC register addresses -----*/
#define _SDRC_BASE_REG_ADDR ( 0x00030980 ) /* reg address: SDRC module base register address */
#define _SDRC_SDBUFD0L_ADDR ( 0x00030980 ) /* reg address: SDRAM Transfer Data Buffer 0H */
#define _SDRC_SDBUFD0H_ADDR ( 0x00030982 ) /* reg address: SDRAM Transfer Data Buffer 0L */
#define _SDRC_SDBUFD1L_ADDR ( 0x00030984 ) /* reg address: SDRAM Transfer Data Buffer 1H */
#define _SDRC_SDBUFD1H_ADDR ( 0x00030986 ) /* reg address: SDRAM Transfer Data Buffer 1L */
#define _SDRC_SDBUFD2L_ADDR ( 0x00030988 ) /* reg address: SDRAM Transfer Data Buffer 2H */
#define _SDRC_SDBUFD2H_ADDR ( 0x0003098A ) /* reg address: SDRAM Transfer Data Buffer 2L */
#define _SDRC_SDBUFD3L_ADDR ( 0x0003098C ) /* reg address: SDRAM Transfer Data Buffer 3H */
#define _SDRC_SDBUFD3H_ADDR ( 0x0003098E ) /* reg address: SDRAM Transfer Data Buffer 3L */
#define _SDRC_SDBUFD4L_ADDR ( 0x00030990 ) /* reg address: SDRAM Transfer Data Buffer 4H */
#define _SDRC_SDBUFD4H_ADDR ( 0x00030992 ) /* reg address: SDRAM Transfer Data Buffer 4L */
#define _SDRC_SDBUFD5L_ADDR ( 0x00030994 ) /* reg address: SDRAM Transfer Data Buffer 5H */
#define _SDRC_SDBUFD5H_ADDR ( 0x00030996 ) /* reg address: SDRAM Transfer Data Buffer 5L */
#define _SDRC_SDBUFD6L_ADDR ( 0x00030998 ) /* reg address: SDRAM Transfer Data Buffer 6H */
#define _SDRC_SDBUFD6H_ADDR ( 0x0003099A ) /* reg address: SDRAM Transfer Data Buffer 6L */
#define _SDRC_SDBUFD7L_ADDR ( 0x0003099C ) /* reg address: SDRAM Transfer Data Buffer 7H */
#define _SDRC_SDBUFD7H_ADDR ( 0x0003099E ) /* reg address: SDRAM Transfer Data Buffer 7L */
#define _SDRC_SDBUFAD1_ADDR ( 0x000309A0 ) /* reg address: SDRAM Transfer Address #1 - Low */
#define _SDRC_SDBUFAD2_ADDR ( 0x000309A2 ) /* reg address: SDRAM Transfer Address #1 - High */
#define _SDRC_SDBUFCTL_ADDR ( 0x000309A4 ) /* reg address: SDRAM Transfer Control */
#define _SDRC_SDMODE_ADDR ( 0x000309A6 ) /* reg address: SDRAM Mode Register */
#define _SDRC_REFCTL_ADDR ( 0x000309A8 ) /* reg address: Refresh Control Register */
#define _SDRC_SDPRTY1_ADDR ( 0x000309AA ) /* reg address: SDRAM Priority Select #1 (CCD Controller) */
#define _SDRC_SDPRTY2_ADDR ( 0x000309AC ) /* reg address: SDRAM Priority Select #2 (Preview Engine) */
#define _SDRC_SDPRTY3_ADDR ( 0x000309AE ) /* reg address: SDRAM Priority Select #3 (Hardware 3A) */
#define _SDRC_SDPRTY4_ADDR ( 0x000309B0 ) /* reg address: SDRAM Priority Select #4 (On Screen Display) */
#define _SDRC_SDPRTY5_ADDR ( 0x000309B2 ) /* reg address: SDRAM Priority Select #5 (External Host) */
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