📄 armcsl_addr_270.h
字号:
#define _OSD_VIDWIN0OFST_ADDR ( 0x0003068C ) /* reg address: Video Window 0 Offset */
#define _OSD_VIDWIN1OFST_ADDR ( 0x0003068E ) /* reg address: Video Window 1 Offset */
#define _OSD_OSDWIN0OFST_ADDR ( 0x00030690 ) /* reg address: OSD Window 0 Offset */
#define _OSD_OSDWIN1OFST_ADDR ( 0x00030692 ) /* reg address: OSD Window 1 Offset */
#define _OSD_VIDWINADH_ADDR ( 0x00030694 ) /* reg address: Video Window 0/1 Address - High */
#define _OSD_VIDWIN0ADL_ADDR ( 0x00030696 ) /* reg address: Video Window 0 Address - Low */
#define _OSD_VIDWIN1ADL_ADDR ( 0x00030698 ) /* reg address: Video Window 1 Address - Low */
#define _OSD_OSDWINADH_ADDR ( 0x0003069A ) /* reg address: OSD Window 0/1 Address - High */
#define _OSD_OSDWIN0ADL_ADDR ( 0x0003069C ) /* reg address: OSD Window 0 Address - Low */
#define _OSD_OSDWIN1ADL_ADDR ( 0x0003069E ) /* reg address: OSD Window 1 Address - Low */
#define _OSD_BASEPX_ADDR ( 0x000306A0 ) /* reg address: Base Pixel X */
#define _OSD_BASEPY_ADDR ( 0x000306A2 ) /* reg address: Base Pixel Y */
#define _OSD_VIDWIN0XP_ADDR ( 0x000306A4 ) /* reg address: Video Window 0 X-Position */
#define _OSD_VIDWIN0YP_ADDR ( 0x000306A6 ) /* reg address: Video Window 0 Y-Position */
#define _OSD_VIDWIN0XL_ADDR ( 0x000306A8 ) /* reg address: Video Window 0 X-Size */
#define _OSD_VIDWIN0YL_ADDR ( 0x000306AA ) /* reg address: Video Window 0 Y-Size */
#define _OSD_VIDWIN1XP_ADDR ( 0x000306AC ) /* reg address: Video Window 1 X-Position */
#define _OSD_VIDWIN1YP_ADDR ( 0x000306AE ) /* reg address: Video Window 1 Y-Position */
#define _OSD_VIDWIN1XL_ADDR ( 0x000306B0 ) /* reg address: Video Window 1 X-Size */
#define _OSD_VIDWIN1YL_ADDR ( 0x000306B2 ) /* reg address: Video Window 1 Y-Size */
#define _OSD_OSDWIN0XP_ADDR ( 0x000306B4 ) /* reg address: OSD Bitmap Window 0 X-Position */
#define _OSD_OSDWIN0YP_ADDR ( 0x000306B6 ) /* reg address: OSD Bitmap Window 0 Y-Position */
#define _OSD_OSDWIN0XL_ADDR ( 0x000306B8 ) /* reg address: OSD Bitmap Window 0 X-Size */
#define _OSD_OSDWIN0YL_ADDR ( 0x000306BA ) /* reg address: OSD Bitmap Window 0 Y-Size */
#define _OSD_OSDWIN1XP_ADDR ( 0x000306BC ) /* reg address: OSD Bitmap Window 1 X-Position */
#define _OSD_OSDWIN1YP_ADDR ( 0x000306BE ) /* reg address: OSD Bitmap Window 1 Y-Position */
#define _OSD_OSDWIN1XL_ADDR ( 0x000306C0 ) /* reg address: OSD Bitmap Window 1 X-Size */
#define _OSD_OSDWIN1YL_ADDR ( 0x000306C2 ) /* reg address: OSD Bitmap Window 1 Y-Size */
#define _OSD_CURXP_ADDR ( 0x000306C4 ) /* reg address: Rectangular Cursor Window X-Position */
#define _OSD_CURYP_ADDR ( 0x000306C6 ) /* reg address: Rectangular Cursor Window Y-Position */
#define _OSD_CURXL_ADDR ( 0x000306C8 ) /* reg address: Rectangular Cursor Window X-Size */
#define _OSD_CURYL_ADDR ( 0x000306CA ) /* reg address: Rectangular Cursor Window Y-Size */
#define _OSD_RSV1_ADDR ( 0x000306CC ) /* reg address: Reserved */
#define _OSD_RSV2_ADDR ( 0x000306CE ) /* reg address: Reserved */
#define _OSD_W0BMP01_ADDR ( 0x000306D0 ) /* reg address: Window 0 Bitmap Value to Palette Map 0/1 */
#define _OSD_W0BMP23_ADDR ( 0x000306D2 ) /* reg address: Window 0 Bitmap Value to Palette Map 2/3 */
#define _OSD_W0BMP45_ADDR ( 0x000306D4 ) /* reg address: Window 0 Bitmap Value to Palette Map 4/5 */
#define _OSD_W0BMP67_ADDR ( 0x000306D6 ) /* reg address: Window 0 Bitmap Value to Palette Map 6/7 */
#define _OSD_W0BMP89_ADDR ( 0x000306D8 ) /* reg address: Window 0 Bitmap Value to Palette Map 8/9 */
#define _OSD_W0BMPAB_ADDR ( 0x000306DA ) /* reg address: Window 0 Bitmap Value to Palette Map A/B */
#define _OSD_W0BMPCD_ADDR ( 0x000306DC ) /* reg address: Window 0 Bitmap Value to Palette Map C/D */
#define _OSD_W0BMPEF_ADDR ( 0x000306DE ) /* reg address: Window 0 Bitmap Value to Palette Map E/F */
#define _OSD_W1BMP01_ADDR ( 0x000306E0 ) /* reg address: Window 1 Bitmap Value to Palette Map 0/1 */
#define _OSD_W1BMP23_ADDR ( 0x000306E2 ) /* reg address: Window 1 Bitmap Value to Palette Map 2/3 */
#define _OSD_W1BMP45_ADDR ( 0x000306E4 ) /* reg address: Window 1 Bitmap Value to Palette Map 4/5 */
#define _OSD_W1BMP67_ADDR ( 0x000306E6 ) /* reg address: Window 1 Bitmap Value to Palette Map 6/7 */
#define _OSD_W1BMP89_ADDR ( 0x000306E8 ) /* reg address: Window 1 Bitmap Value to Palette Map 8/9 */
#define _OSD_W1BMPAB_ADDR ( 0x000306EA ) /* reg address: Window 1 Bitmap Value to Palette Map A/B */
#define _OSD_W1BMPCD_ADDR ( 0x000306EC ) /* reg address: Window 1 Bitmap Value to Palette Map C/D */
#define _OSD_W1BMPEF_ADDR ( 0x000306EE ) /* reg address: Window 1 Bitmap Value to Palette Map E/F */
#define _OSD_RSV3_ADDR ( 0x000306F2 ) /* reg address: Reserved */
#define _OSD_MISCCTL_ADDR ( 0x000306F4 ) /* reg address: Miscellaneous Control */
#define _OSD_CLUTRAMYCB_ADDR ( 0x000306F6 ) /* reg address: CLUT RAM Y/Cb Setup */
#define _OSD_CLUTRAMCR_ADDR ( 0x000306F8 ) /* reg address: CLUT RAM Cr/Mapping Setup */
#define _OSD_PPVWIN0ADH_ADDR ( 0x000306FC ) /* reg address: Ping-Pong Video Window 0 Address (High) */
#define _OSD_PPVWIN0ADL_ADDR ( 0x000306FE ) /* reg address: Ping-Pong Video Window 0 Address (Low) */
/*------------------------------------------------------------*/
/*----- Constant definitions for CCDC register addresses -----*/
#define _CCDC_BASE_REG_ADDR ( 0x00030700 ) /* reg address: CCDC module base address */
#define _CCDC_SYNCEN_ADDR ( 0x00030700 ) /* reg address: Synchronization Enable */
#define _CCDC_MODESET_ADDR ( 0x00030702 ) /* reg address: Mode Setup */
#define _CCDC_HDWIDTH_ADDR ( 0x00030704 ) /* reg address: HD pulse width */
#define _CCDC_VDWIDTH_ADDR ( 0x00030706 ) /* reg address: VD pulse width */
#define _CCDC_PPLN_ADDR ( 0x00030708 ) /* reg address: Pixels per line */
#define _CCDC_LPFR_ADDR ( 0x0003070A ) /* reg address: Lines per frame */
#define _CCDC_SPH_ADDR ( 0x0003070C ) /* reg address: Start pixel horizontal */
#define _CCDC_NPH_ADDR ( 0x0003070E ) /* reg address: Number of pixels horizontal */
#define _CCDC_SLV0_ADDR ( 0x00030710 ) /* reg address: Start line vertical - field 0 */
#define _CCDC_SLV1_ADDR ( 0x00030712 ) /* reg address: Start line vertical - field 1 */
#define _CCDC_NLV_ADDR ( 0x00030714 ) /* reg address: Number of lines vertical */
#define _CCDC_CULH_ADDR ( 0x00030716 ) /* reg address: Culling - horizontal */
#define _CCDC_CULV_ADDR ( 0x00030718 ) /* reg address: Culling - vertical */
#define _CCDC_HSIZE_ADDR ( 0x0003071A ) /* reg address: Horizontal size */
#define _CCDC_SDOFST_ADDR ( 0x0003071C ) /* reg address: SDRAM Line Offset */
#define _CCDC_STADRH_ADDR ( 0x0003071E ) /* reg address: SDRAM Address #1 - high */
#define _CCDC_STADRL_ADDR ( 0x00030720 ) /* reg address: SDRAM Address #2 - low */
#define _CCDC_CLAMP_ADDR ( 0x00030722 ) /* reg address: CCD Data Clamping */
#define _CCDC_DCSUB_ADDR ( 0x00030724 ) /* reg address: DC Clamp */
#define _CCDC_COLPTN_ADDR ( 0x00030726 ) /* reg address: CCD Color Pattern */
#define _CCDC_BLKCMP1_ADDR ( 0x00030728 ) /* reg address: Black Compensation #1 */
#define _CCDC_BLKCMP2_ADDR ( 0x0003072A ) /* reg address: Black Compensation #2 */
#define _CCDC_MEDFILT_ADDR ( 0x0003072C ) /* reg address: CCD Median Filter */
#define _CCDC_GAIN_ADDR ( 0x0003072E ) /* reg address: CCD Gain Adjustment */
#define _CCDC_OFFSET_ADDR ( 0x00030730 ) /* reg address: CCD Offset Adjustment */
#define _CCDC_OUTTH_ADDR ( 0x00030732 ) /* reg address: Output Clipping Threshold */
#define _CCDC_OUTCLIP_ADDR ( 0x00030734 ) /* reg address: Output Clipping Value */
#define _CCDC_VDINT0_ADDR ( 0x00030736 ) /* reg address: VD Interrupt #0 */
#define _CCDC_VDINT1_ADDR ( 0x00030738 ) /* reg address: VD Interrupt #1 */
#define _CCDC_SHUT_ADDR ( 0x0003073A ) /* reg address: CCD Shutter */
#define _CCDC_GAMMA_ADDR ( 0x0003073C ) /* reg address: CCD Gamma */
#define _CCDC_REC656IF_ADDR ( 0x0003073E ) /* reg address: CCIR 656 Control */
#define _CCDC_CCDCFG_ADDR ( 0x00030740 ) /* reg address: CCD Configuration */
/*------------------------------------------------------------*/
/*----- Constant definitions for PREV register addresses -----*/
#define _PREV_BASE_REG_ADDR ( 0x00030780 ) /* reg address: PREV module base address */
#define _PREV_PVEN_ADDR ( 0x00030780 ) /* reg address: Preview Enable Register */
#define _PREV_PVSET1_ADDR ( 0x00030782 ) /* reg address: Preview Setup Register #1 */
#define _PREV_RADRH_ADDR ( 0x00030784 ) /* reg address: SDRAM Read Address - high order bits */
#define _PREV_RADRL_ADDR ( 0x00030786 ) /* reg address: SDRAM Read Address - low order bits */
#define _PREV_WADRH_ADDR ( 0x00030788 ) /* reg address: SDRAM Write Address - high order bits */
#define _PREV_WADRL_ADDR ( 0x0003078A ) /* reg address: SDRAM Write Address - low order bits */
#define _PREV_HSTART_ADDR ( 0x0003078C ) /* reg address: Start pixel horizontal (for CCD input) Horizontal Size in SDRAM (for SDRAM input) */
#define _PREV_HSIZE_ADDR ( 0x0003078E ) /* reg address: Number of pixels horizontal */
#define _PREV_VSTART_ADDR ( 0x00030790 ) /* reg address: Start line vertical */
#define _PREV_VSIZE_ADDR ( 0x00030792 ) /* reg address: Number of pixels vertical */
#define _PREV_PVSET2_ADDR ( 0x00030794 ) /* reg address: Preview Setup Register #2 */
#define _PREV_NFILT_ADDR ( 0x00030796 ) /* reg address: Noise Filter Definition Register */
#define _PREV_DGAIN_ADDR ( 0x00030798 ) /* reg address: Digital Gain Register */
#define _PREV_WBGAIN0_ADDR ( 0x0003079A ) /* reg address: White Balance Gain register #0 */
#define _PREV_WBGAIN1_ADDR ( 0x0003079C ) /* reg address: White Balance Gain register #1 */
#define _PREV_SMTH_ADDR ( 0x0003079E ) /* reg address: Smoothing Definition register */
#define _PREV_HRSZ_ADDR ( 0x000307A0 ) /* reg address: Horizontal Resize Register */
#define _PREV_VRSZ_ADDR ( 0x000307A2 ) /* reg address: Vertical Resize Register */
#define _PREV_BLOFST0_ADDR ( 0x000307A4 ) /* reg address: Black Level Offset Adjust #0 */
#define _PREV_BLOFST1_ADDR ( 0x000307A6 ) /* reg address: Black Level Offset Adjust #1 */
#define _PREV_MTXGAIN0_ADDR ( 0x000307A8 ) /* reg address: Matrix Gain register #0 */
#define _PREV_MTXGAIN1_ADDR ( 0x000307AA ) /* reg address: Matrix Gain register #1 */
#define _PREV_MTXGAIN2_ADDR ( 0x000307AC ) /* reg address: Matrix Gain register #2 */
#define _PREV_MTXGAIN3_ADDR ( 0x000307AE ) /* reg address: Matrix Gain register #3 */
#define _PREV_MTXGAIN4_ADDR ( 0x000307B0 ) /* reg address: Matrix Gain register #4 */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -