armcsl_addr_270.h

dm270 source code

#define _MMCSD_MMCST1_ADDR              ( 0x00030486 )
#define _MMCSD_MMCIE_ADDR               ( 0x00030488 )
#define _MMCSD_MMCTOR_ADDR              ( 0x0003048A )
#define _MMCSD_MMCTOD_ADDR              ( 0x0003048C )
#define _MMCSD_MMCBLEN_ADDR             ( 0x0003048E )
#define _MMCSD_MMCNBLK_ADDR             ( 0x00030490 )
#define _MMCSD_MMCNBLC_ADDR             ( 0x00030492 )
#define _MMCSD_MMCDRR_ADDR              ( 0x00030494 )
#define _MMCSD_MMCDXR_ADDR              ( 0x00030496 )
#define _MMCSD_MMCCMD_ADDR              ( 0x00030498 )
#define _MMCSD_MMCARGL_ADDR             ( 0x0003049A )
#define _MMCSD_MMCARGH_ADDR             ( 0x0003049C )
#define _MMCSD_MMCRSP0_ADDR             ( 0x0003049E )
#define _MMCSD_MMCRSP1_ADDR             ( 0x000304A0 )
#define _MMCSD_MMCRSP2_ADDR             ( 0x000304A2 )
#define _MMCSD_MMCRSP3_ADDR             ( 0x000304A4 )
#define _MMCSD_MMCRSP4_ADDR             ( 0x000304A6 )
#define _MMCSD_MMCRSP5_ADDR             ( 0x000304A8 )
#define _MMCSD_MMCRSP6_ADDR             ( 0x000304AA )
#define _MMCSD_MMCRSP7_ADDR             ( 0x000304AC )
#define _MMCSD_MMCDRSP_ADDR             ( 0x000304AE )
#define _MMCSD_MMCETOK_ADDR             ( 0x000304B0 )
#define _MMCSD_MMCCIDX_ADDR             ( 0x000304B2 )
#define _MMCSD_MMCCKC_ADDR              ( 0x000304B4 )
#define _MMCSD_MMCTORC_ADDR             ( 0x000304B6 )
#define _MMCSD_MMCTODC_ADDR             ( 0x000304B8 )
#define _MMCSD_MMCBLNC_ADDR             ( 0x000304BA )
#define _MMCSD_DMATRG_ADDR              ( 0x000304BC )
#define _MMCSD_DMAMODE_ADDR             ( 0x000304BE )
#define _MMCSD_DMAAD0_ADDR              ( 0x000304C0 )
#define _MMCSD_DMAAD1_ADDR              ( 0x000304C2 )
#define _MMCSD_DMASTAT0_ADDR            ( 0x000304C4 )
#define _MMCSD_DMASTAT1_ADDR            ( 0x000304C6 )
#define _MMCSD_DMATOR_ADDR              ( 0x000304C8 )
#define _MMCSD_SDIOCTL_ADDR             ( 0x000304CA )
#define _MMCSD_SDIOST0_ADDR             ( 0x000304CC )
#define _MMCSD_SDIOIEN_ADDR             ( 0x000304CE )
#define _MMCSD_SDIOIST_ADDR             ( 0x000304D0 )

/*------------------------------------------------------------*/
/*----- Constant definitions for INTC register addresses -----*/
#define _INTC_BASE_REG_ADDR            ( 0x00030500 ) /* reg address: INTC module base address                      */
#define _INTC_FIQ0_ADDR                ( 0x00030500 ) /* reg address: FIQ Interrupt Flag Register #0                */
#define _INTC_FIQ1_ADDR                ( 0x00030502 ) /* reg address: FIQ Interrupt Flag Register #1                */
#define _INTC_FIQ2_ADDR                ( 0x00030504 ) /* reg address: FIQ Interrupt Flag Register #2                */
#define _INTC_IRQ0_ADDR                ( 0x00030508 ) /* reg address: IRQ Interrupt Flag Register #0                */
#define _INTC_IRQ1_ADDR                ( 0x0003050A ) /* reg address: IRQ Interrupt Flag Register #1                */
#define _INTC_IRQ2_ADDR                ( 0x0003050C ) /* reg address: IRQ Interrupt Flag Register #2                */
#define _INTC_FIQENTRY0_ADDR           ( 0x00030510 ) /* reg address: FIQ Entry Address Register #0                 */
#define _INTC_FIQENTRY1_ADDR           ( 0x00030512 ) /* reg address: FIQ Entry Address Register #1                 */
#define _INTC_IRQENTRY0_ADDR           ( 0x00030518 ) /* reg address: IRQ Entry Address Register #0                 */
#define _INTC_IRQENTRY1_ADDR           ( 0x0003051A ) /* reg address: IRQ Entry Address Register #1                 */
#define _INTC_FISEL0_ADDR              ( 0x00030520 ) /* reg address: FIQ select register #0                        */
#define _INTC_FISEL1_ADDR              ( 0x00030522 ) /* reg address: FIQ select register #1                        */
#define _INTC_FISEL2_ADDR              ( 0x00030524 ) /* reg address: FIQ select register #2                        */
#define _INTC_EINT0_ADDR               ( 0x00030528 ) /* reg address: Interrupt Enable Register #0                  */
#define _INTC_EINT1_ADDR               ( 0x0003052A ) /* reg address: Interrupt Enable Register #1                  */
#define _INTC_EINT2_ADDR               ( 0x0003052C ) /* reg address: Interrupt Enable Register #2                  */
#define _INTC_INTRAW_ADDR              ( 0x00030530 ) /* reg address: Interrupt Raw Register                        */
#define _INTC_EABASE0_ADDR             ( 0x00030538 ) /* reg address: Entry Table Base Address Register #0          */
#define _INTC_EABASE1_ADDR             ( 0x0003053A ) /* reg address: Entry Table Base Address Register #1          */
#define _INTC_INTPRI00_ADDR            ( 0x00030540 ) /* reg address: Interrupt Priority Register #0                */
#define _INTC_INTPRI01_ADDR            ( 0x00030542 ) /* reg address: Interrupt Priority Register #1                */
#define _INTC_INTPRI02_ADDR            ( 0x00030544 ) /* reg address: Interrupt Priority Register #2                */
#define _INTC_INTPRI03_ADDR            ( 0x00030546 ) /* reg address: Interrupt Priority Register #3                */
#define _INTC_INTPRI04_ADDR            ( 0x00030548 ) /* reg address: Interrupt Priority Register #4                */
#define _INTC_INTPRI05_ADDR            ( 0x0003054A ) /* reg address: Interrupt Priority Register #5                */
#define _INTC_INTPRI06_ADDR            ( 0x0003054C ) /* reg address: Interrupt Priority Register #6                */
#define _INTC_INTPRI07_ADDR            ( 0x0003054E ) /* reg address: Interrupt Priority Register #7                */
#define _INTC_INTPRI08_ADDR            ( 0x00030550 ) /* reg address: Interrupt Priority Register #8                */
#define _INTC_INTPRI09_ADDR            ( 0x00030552 ) /* reg address: Interrupt Priority Register #9                */
#define _INTC_INTPRI10_ADDR            ( 0x00030554 ) /* reg address: Interrupt Priority Register #10               */
#define _INTC_INTPRI11_ADDR            ( 0x00030556 ) /* reg address: Interrupt Priority Register #11               */
#define _INTC_INTPRI12_ADDR            ( 0x00030558 ) /* reg address: Interrupt Priority Register #12               */
#define _INTC_INTPRI13_ADDR            ( 0x0003055A ) /* reg address: Interrupt Priority Register #13               */
#define _INTC_INTPRI14_ADDR            ( 0x0003055C ) /* reg address: Interrupt Priority Register #14               */
#define _INTC_INTPRI15_ADDR            ( 0x0003055E ) /* reg address: Interrupt Priority Register #15               */
#define _INTC_INTPRI16_ADDR            ( 0x00030560 ) /* reg address: Interrupt Priority Register #16               */
#define _INTC_INTPRI17_ADDR            ( 0x00030562 ) /* reg address: Interrupt Priority Register #17               */
#define _INTC_INTPRI18_ADDR            ( 0x00030564 ) /* reg address: Interrupt Priority Register #18               */
#define _INTC_INTPRI19_ADDR            ( 0x00030566 ) /* reg address: Interrupt Priority Register #19               */

/*-----------------------------------------------------------*/
/*----- Constant definitions for GIO register addresses -----*/
#define _GIO_BASE_REG_ADDR            ( 0x00030580 ) /* reg address: GIO module base address                       */
#define _GIO_DIR0_ADDR                ( 0x00030580 ) /* reg address: GIO Direction Register 0                      */
#define _GIO_DIR1_ADDR                ( 0x00030582 ) /* reg address: GIO Direction Register 1                      */
#define _GIO_DIR2_ADDR                ( 0x00030584 ) /* reg address: GIO Direction Register 2                      */
#define _GIO_INV0_ADDR                ( 0x00030586 ) /* reg address: GIO Inversion Register 0                      */
#define _GIO_INV1_ADDR                ( 0x00030588 ) /* reg address: GIO Inversion Register 1                      */
#define _GIO_INV2_ADDR                ( 0x0003058A ) /* reg address: GIO Inversion Register 2                      */
#define _GIO_BITSET0_ADDR             ( 0x0003058C ) /* reg address: GIO Bit Set Register 0                        */
#define _GIO_BITSET1_ADDR             ( 0x0003058E ) /* reg address: GIO Bit Set Register 1                        */
#define _GIO_BITSET2_ADDR             ( 0x00030590 ) /* reg address: GIO Bit Set Register 2                        */
#define _GIO_BITCLR0_ADDR             ( 0x00030592 ) /* reg address: GIO Bit Clear Register 0                      */
#define _GIO_BITCLR1_ADDR             ( 0x00030594 ) /* reg address: GIO Bit Clear Register 1                      */
#define _GIO_BITCLR2_ADDR             ( 0x00030596 ) /* reg address: GIO Bit Clear Register 2                      */
#define _GIO_IRQPORT_ADDR             ( 0x00030598 ) /* reg address: GIO IRQ Port Setting Register                 */
#define _GIO_IRQEDGE_ADDR             ( 0x0003059A ) /* reg address: GIO IRQ Edge Setting Register                 */
#define _GIO_CHAT0_ADDR               ( 0x0003059C ) /* reg address: GIO Chatter Setting Register 0                */
#define _GIO_CHAT1_ADDR               ( 0x0003059E ) /* reg address: GIO Chatter Setting Register 1                */
#define _GIO_CHAT2_ADDR               ( 0x000305A0 ) /* reg address: GIO Chatter Setting Register 2                */
#define _GIO_NCHAT_ADDR               ( 0x000305A2 ) /* reg address: GIO Chatter Value Register                    */
#define _GIO_FSEL0_ADDR               ( 0x000305A4 ) /* reg address: GIO Function Select Register 0                */
#define _GIO_FSEL1_ADDR               ( 0x000305A6 ) /* reg address: GIO Function Select Register 1                */

/*------------------------------------------------------------*/
/*----- Constant definitions for DSPC register addresses -----*/
#define _DSPC_BASE_REG_ADDR            ( 0x00030600 ) /* reg address: DSPC module base address                      */
#define _DSPC_HPIBCTL_ADDR             ( 0x00030600 ) /* reg address: HPIB Control Register                         */
#define _DSPC_HPIBSTAT_ADDR            ( 0x00030602 ) /* reg address: HPIB Status Register                          */

/*-----------------------------------------------------------*/
/*----- Constant definitions for OSD register addresses -----*/
#define _OSD_BASE_REG_ADDR            ( 0x00030680 ) /* reg address: OSD module base address                                 */
#define _OSD_OSDMODE_ADDR             ( 0x00030680 ) /* reg address: OSD Mode Setup                                          */
#define _OSD_VIDWINMD_ADDR            ( 0x00030682 ) /* reg address: Video Window Mode Setup                                 */
#define _OSD_OSDWIN0MD_ADDR           ( 0x00030684 ) /* reg address: OSD Window 0 Mode Setup                                 */
#define _OSD_OSDWIN1MD_ADDR           ( 0x00030686 ) /* reg address: OSD Window 1 Mode Setup                                 */
#define _OSD_OSDATRMD_ADDR            ( 0x00030686 ) /* reg address: OSD Attribute Window Mode Setup                         */
#define _OSD_RECTCUR_ADDR             ( 0x00030688 ) /* reg address: Rectangular Cursor Setup                                */
#define _OSD_RSV0_ADDR                ( 0x0003068A ) /* reg address: Reserved                                                */