armcsl_addr_270.h

dm270 source code

/*  
 *  Copyright 2002 by Texas Instruments Incorporated. 
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2002 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* PROJECT....... DM270 ARM Chip Support Library
*
  !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  !!!!!!!!!!!!!  WARNING: THIS IS AN AUTO-GENERATED FILE  !!!!!!!!!!!!!!!
  !!!!!!!!!!!!!           DO NOT EDIT THIS FILE.          !!!!!!!!!!!!!!!
  !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*
*------------------------------------------------------------------------------
*   CREATED:       March, 2002
*------------------------------------------------------------------------------*
*
*
\******************************************************************************/

/*------------------------------------------------------------*/
/*----- Constant definitions for TMR0 register addresses -----*/
#define _TMR0_BASE_REG_ADDR            ( 0x00030000 ) /* reg address: TMR0 module base address                      */
#define _TMR0_TMMD0_ADDR               ( 0x00030000 ) /* reg address: Timer 0 Mode                                  */
#define _TMR0_TMRSV0_ADDR              ( 0x00030002 ) /* reg address: Reserved                                      */
#define _TMR0_TMPRSCL0_ADDR            ( 0x00030004 ) /* reg address: Timer 0 Prescalar                             */
#define _TMR0_TMDIV0_ADDR              ( 0x00030006 ) /* reg address: Timer 0 Divisor (count)                       */
#define _TMR0_TMTRG0_ADDR              ( 0x00030008 ) /* reg address: Timer 0 One-Shot Trigger                      */
#define _TMR0_TMCNT0_ADDR              ( 0x0003000A ) /* reg address: Timer 0 Count                                 */

/*------------------------------------------------------------*/
/*----- Constant definitions for TMR1 register addresses -----*/
#define _TMR1_BASE_REG_ADDR            ( 0x00030080 ) /* reg address: TMR1 module base address                      */
#define _TMR1_TMMD1_ADDR               ( 0x00030080 ) /* reg address: Timer 1 Mode                                  */
#define _TMR1_TMRSV1_ADDR              ( 0x00030082 ) /* reg address: Reserved                                      */
#define _TMR1_TMPRSCL1_ADDR            ( 0x00030084 ) /* reg address: Timer 1 Prescalar                             */
#define _TMR1_TMDIV1_ADDR              ( 0x00030086 ) /* reg address: Timer 1 Divisor (count)                       */
#define _TMR1_TMTRG1_ADDR              ( 0x00030088 ) /* reg address: Timer 1 One-Shot Trigger                      */
#define _TMR1_TMCNT1_ADDR              ( 0x0003008A ) /* reg address: Timer 1 Count                                 */

/*------------------------------------------------------------*/
/*----- Constant definitions for TMR2 register addresses -----*/
#define _TMR2_BASE_REG_ADDR            ( 0x00030100 ) /* reg address: TMR2 module base address                      */
#define _TMR2_TMMD2_ADDR               ( 0x00030100 ) /* reg address: Timer 2 Mode                                  */
#define _TMR2_TMRSV2_ADDR              ( 0x00030102 ) /* reg address: Reserved                                      */
#define _TMR2_TMPRSCL2_ADDR            ( 0x00030104 ) /* reg address: Timer 2 Prescalar                             */
#define _TMR2_TMDIV2_ADDR              ( 0x00030106 ) /* reg address: Timer 2 Divisor (count)                       */
#define _TMR2_TMTRG2_ADDR              ( 0x00030108 ) /* reg address: Timer 2 One-Shot Trigger                      */
#define _TMR2_TMCNT2_ADDR              ( 0x0003010A ) /* reg address: Timer 2 Count                                 */

/*------------------------------------------------------------*/
/*----- Constant definitions for TMR3 register addresses -----*/
#define _TMR3_BASE_REG_ADDR            ( 0x00030180 ) /* reg address: TMR3 module base address                      */
#define _TMR3_TMMD3_ADDR               ( 0x00030180 ) /* reg address: Timer 3 Mode                                  */
#define _TMR3_TMRSV3_ADDR              ( 0x00030182 ) /* reg address: Reserved                                      */
#define _TMR3_TMPRSCL3_ADDR            ( 0x00030184 ) /* reg address: Timer 3 Prescalar                             */
#define _TMR3_TMDIV3_ADDR              ( 0x00030186 ) /* reg address: Timer 3 Divisor (count)                       */
#define _TMR3_TMTRG3_ADDR              ( 0x00030188 ) /* reg address: Timer 3 One-Shot Trigger                      */
#define _TMR3_TMCNT3_ADDR              ( 0x0003018A ) /* reg address: Timer 3 Count                                 */

/*-----------------------------------------------------------*/
/*----- Constant definitions for SP0 register addresses -----*/
#define _SP0_BASE_REG_ADDR            ( 0x00030200 ) /* reg address: SP0 module base address                       */
#define _SP0_TXDATA0_ADDR             ( 0x00030200 ) /* reg address: SP0 Transmit Data Register                    */
#define _SP0_RXDATA0_ADDR             ( 0x00030202 ) /* reg address: SP0 Receive Data Register                     */
#define _SP0_SIOEN0_ADDR              ( 0x00030204 ) /* reg address: SP0 Transmit Enable                           */
#define _SP0_SIOMODE0_ADDR            ( 0x00030206 ) /* reg address: SP0 Mode                                      */
#define _SP0_DMATRG0_ADDR             ( 0x00030208 ) /* reg address: SP0 DMA Trigger                               */
#define _SP0_DMAMODE0_ADDR            ( 0x0003020A ) /* reg address: SP0 DMA Mode                                  */
#define _SP0_DMASTADL0_ADDR           ( 0x0003020C ) /* reg address: SP0 DMA SDRAM Start Address - low             */
#define _SP0_DMASTADH0_ADDR           ( 0x0003020E ) /* reg address: SP0 DMA SDRAM Start Address - high            */
#define _SP0_DMASTAT0_ADDR            ( 0x00030210 ) /* reg address: SP0 DMA Status                                */

/*-----------------------------------------------------------*/
/*----- Constant definitions for SP1 register addresses -----*/
#define _SP1_BASE_REG_ADDR            ( 0x00030280 ) /* reg address: SP1 module base address                       */
#define _SP1_TXDATA1_ADDR             ( 0x00030280 ) /* reg address: SP1 Transmit Data Register                    */
#define _SP1_RXDATA1_ADDR             ( 0x00030282 ) /* reg address: SP1 Receive Data Register                     */
#define _SP1_SIOEN1_ADDR              ( 0x00030284 ) /* reg address: SP1 Transmit Enable                           */
#define _SP1_SIOMODE1_ADDR            ( 0x00030286 ) /* reg address: SP1 Mode                                      */

/*-------------------------------------------------------------*/
/*----- Constant definitions for UART0 register addresses -----*/
#define _UART0_BASE_REG_ADDR            ( 0x00030300 ) /* reg address: UART0 module base address                     */
#define _UART0_DTRR0_ADDR               ( 0x00030300 ) /* reg address: UART0 Data Transmit/Receive Register          */
#define _UART0_BRSR0_ADDR               ( 0x00030302 ) /* reg address: UART0 Bit Rate Set Register                   */
#define _UART0_MSR0_ADDR                ( 0x00030304 ) /* reg address: UART0 Mode Setup Register                     */
#define _UART0_RFCR0_ADDR               ( 0x00030306 ) /* reg address: UART0 Receive FIFO Control Register           */
#define _UART0_TFCR0_ADDR               ( 0x00030308 ) /* reg address: UART0 Transmit FIFO Control Register          */
#define _UART0_LCR0_ADDR                ( 0x0003030A ) /* reg address: UART0 Line Control Register                   */
#define _UART0_SR0_ADDR                 ( 0x0003030C ) /* reg address: UART0 Status Register                         */

/*-------------------------------------------------------------*/
/*----- Constant definitions for UART1 register addresses -----*/
#define _UART1_BASE_REG_ADDR            ( 0x00030380 ) /* reg address: UART1 module base address                     */
#define _UART1_DTRR1_ADDR               ( 0x00030380 ) /* reg address: UART1 Data Transmit/Receive Register          */
#define _UART1_BRSR1_ADDR               ( 0x00030382 ) /* reg address: UART1 Bit Rate Set Register                   */
#define _UART1_MSR1_ADDR                ( 0x00030384 ) /* reg address: UART1 Mode Setup Register                     */
#define _UART1_RFCR1_ADDR               ( 0x00030386 ) /* reg address: UART1 Receive FIFO Control Register           */
#define _UART1_TFCR1_ADDR               ( 0x00030388 ) /* reg address: UART1 Transmit FIFO Control Register          */
#define _UART1_LCR1_ADDR                ( 0x0003038A ) /* reg address: UART1 Line Control Register                   */
#define _UART1_SR1_ADDR                 ( 0x0003038C ) /* reg address: UART1 Status Register                         */

/*-----------------------------------------------------------*/
/*----- Constant definitions for WDT register addresses -----*/
#define _WDT_BASE_REG_ADDR            ( 0x00030400 ) /* reg address: WDT module base address                       */
#define _WDT_WDTMD_ADDR               ( 0x00030400 ) /* reg address: Watch Dog Timer Mode                          */
#define _WDT_WDTRST_ADDR              ( 0x00030402 ) /* reg address: Watch Dog Timer Reset                         */
#define _WDT_WDTPRSCL_ADDR            ( 0x00030404 ) /* reg address: Watch Dog Timer Prescalar                     */
#define _WDT_WDTDIV_ADDR              ( 0x00030406 ) /* reg address: Watch Dog Timer Divisor (count)               */
#define _WDT_WDTEXRST_ADDR            ( 0x00030408 ) /* reg address: Watch Dog Timer External Reset                */

/*-------------------------------------------------------------*/
/*----- Constant definitions for MMCSD register addresses -----*/
#define _MMCSD_BASE_REG_ADDR            ( 0x00030480 ) /* reg address: MMCSD module base address                     */
#define _MMCSD_MMCCTL_ADDR              ( 0x00030480 ) /* reg address: MMC Function Clock Control Register           */
#define _MMCSD_MMCCLK_ADDR              ( 0x00030482 )
#define _MMCSD_MMCST0_ADDR              ( 0x00030484 )