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📄 csl_tmr3hal_270.h

📁 dm270 source code
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/*    *  Copyright 2001 by Texas Instruments Incorporated. *  All rights reserved. Property of Texas Instruments Incorporated. *  Restricted rights to use, duplicate or disclose this code are *  granted through contract. *//******************************************************************************\*           Copyright (C) 2001 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* MODULE.NAME... TMR3 - HAL configuration module* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_tmr3hal_270.h* PROJECT....... ARM Chip Support Library* COMPONENT..... HAL* IMPORTS....... *------------------------------------------------------------------------------* HISTORY:*   CREATED:       12/06/2001 *------------------------------------------------------------------------------* DESCRIPTION:  (CHIP memory mapped register definitions)***\******************************************************************************//*-----------------------------------------------------------------------------------** Register Macros for TMR3:*------------------------------------------------------------------------------------*//*------------------------------------------------------------------------------** Register Macros for TMR3 TMMD3 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR3_TMMD3_GET()			_REG_GET(_TMR3_TMMD3_ADDR)#define _TMR3_TMMD3_SET(Val)			_REG_SET(_TMR3_TMMD3_ADDR, Val)#define _TMR3_TMMD3_AOI(AND,OR,INV)		_REG_AOI(_TMR3_TMMD3_ADDR,AND,OR,INV)#define _TMR3_TMMD3_FGET(Field)			_FIELD_GET(_TMR3_TMMD3_ADDR, _TMR3_TMMD3_##Field##)#define _TMR3_TMMD3_FSET(Field, Val)		_FIELD_SET(_TMR3_TMMD3_ADDR, _TMR3_TMMD3_##Field##, Val)#define _TMR3_TMMD3_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_TMR3_TMMD3_ADDR, _TMR3_TMMD3_##Field##, AND, OR, INV)#define _TMR3_TMMD3_TEST_SHIFT		(2)#define _TMR3_TMMD3_TEST_MK(n)		(((Uint16)(n) & 0x003fu) << _TMR3_TMMD3_TEST_SHIFT)#define _TMR3_TMMD3_TEST_MASK			(_TMR3_TMMD3_TEST_MK(0x003fu))#define _TMR3_TMMD3_TEST_CLR			(~(_TMR3_TMMD3_TEST_MASK))#define _TMR3_TMMD3_MODE_SHIFT		(0)#define _TMR3_TMMD3_MODE_MK(n)		((Uint16)(n) & 0x0003u) #define _TMR3_TMMD3_MODE_MASK			(_TMR3_TMMD3_MODE_MK(0x0003u))#define _TMR3_TMMD3_MODE_CLR			(~(_TMR3_TMMD3_MODE_MASK))/*------------------------------------------------------------------------------** Register Macros for TMR3 TMRSV3 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR3_TMRSV3_GET()			_REG_GET(_TMR3_TMRSV3_ADDR)#define _TMR3_TMRSV3_SET(Val)			_REG_SET(_TMR3_TMRSV3_ADDR, Val)#define _TMR3_TMRSV3_AOI(AND,OR,INV)		_REG_AOI(_TMR3_TMRSV3_ADDR,AND,OR,INV)/*------------------------------------------------------------------------------** Register Macros for TMR3 TMPRSCL3 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR3_TMPRSCL3_GET()			_REG_GET(_TMR3_TMPRSCL3_ADDR)#define _TMR3_TMPRSCL3_SET(Val)			_REG_SET(_TMR3_TMPRSCL3_ADDR, Val)#define _TMR3_TMPRSCL3_AOI(AND,OR,INV)		_REG_AOI(_TMR3_TMPRSCL3_ADDR,AND,OR,INV)#define _TMR3_TMPRSCL3_FGET(Field)			_FIELD_GET(_TMR3_TMPRSCL3_ADDR, _TMR3_TMPRSCL3_##Field##)#define _TMR3_TMPRSCL3_FSET(Field, Val)		_FIELD_SET(_TMR3_TMPRSCL3_ADDR, _TMR3_TMPRSCL3_##Field##, Val)#define _TMR3_TMPRSCL3_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_TMR3_TMPRSCL3_ADDR, _TMR3_TMPRSCL3_##Field##, AND, OR, INV)#define _TMR3_TMPRSCL3_PRSCL_SHIFT		(0)#define _TMR3_TMPRSCL3_PRSCL_MK(n)		((Uint16)(n) & 0x03ffu) #define _TMR3_TMPRSCL3_PRSCL_MASK			(_TMR3_TMPRSCL3_PRSCL_MK(0x03ffu))#define _TMR3_TMPRSCL3_PRSCL_CLR			(~(_TMR3_TMPRSCL3_PRSCL_MASK))/*------------------------------------------------------------------------------** Register Macros for TMR3 TMDIV3 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR3_TMDIV3_GET()			_REG_GET(_TMR3_TMDIV3_ADDR)#define _TMR3_TMDIV3_SET(Val)			_REG_SET(_TMR3_TMDIV3_ADDR, Val)#define _TMR3_TMDIV3_AOI(AND,OR,INV)		_REG_AOI(_TMR3_TMDIV3_ADDR,AND,OR,INV)/*------------------------------------------------------------------------------** Register Macros for TMR3 TMTRG3 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR3_TMTRG3_GET()			_REG_GET(_TMR3_TMTRG3_ADDR)#define _TMR3_TMTRG3_SET(Val)			_REG_SET(_TMR3_TMTRG3_ADDR, Val)#define _TMR3_TMTRG3_AOI(AND,OR,INV)		_REG_AOI(_TMR3_TMTRG3_ADDR,AND,OR,INV)#define _TMR3_TMTRG3_FGET(Field)			_FIELD_GET(_TMR3_TMTRG3_ADDR, _TMR3_TMTRG3_##Field##)#define _TMR3_TMTRG3_FSET(Field, Val)		_FIELD_SET(_TMR3_TMTRG3_ADDR, _TMR3_TMTRG3_##Field##, Val)#define _TMR3_TMTRG3_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_TMR3_TMTRG3_ADDR, _TMR3_TMTRG3_##Field##, AND, OR, INV)#define _TMR3_TMTRG3_TRG_SHIFT		(0)#define _TMR3_TMTRG3_TRG_MK(n)		((Uint16)(n) & 0x0001u) #define _TMR3_TMTRG3_TRG_MASK			(_TMR3_TMTRG3_TRG_MK(0x0001u))#define _TMR3_TMTRG3_TRG_CLR			(~(_TMR3_TMTRG3_TRG_MASK))/*------------------------------------------------------------------------------** Register Macros for TMR3 TMCNT3 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR3_TMCNT3_GET()			_REG_GET(_TMR3_TMCNT3_ADDR)#define _TMR3_TMCNT3_SET(Val)			_REG_SET(_TMR3_TMCNT3_ADDR, Val)#define _TMR3_TMCNT3_AOI(AND,OR,INV)		_REG_AOI(_TMR3_TMCNT3_ADDR,AND,OR,INV)

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