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📄 csl_tmr1hal_270.h

📁 dm270 source code
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/*    *  Copyright 2001 by Texas Instruments Incorporated. *  All rights reserved. Property of Texas Instruments Incorporated. *  Restricted rights to use, duplicate or disclose this code are *  granted through contract. *//******************************************************************************\*           Copyright (C) 2001 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* MODULE.NAME... TMR1 - HAL configuration module* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_tmr1hal_270.h* PROJECT....... ARM Chip Support Library* COMPONENT..... HAL* IMPORTS....... *------------------------------------------------------------------------------* HISTORY:*   CREATED:       12/06/2001 *------------------------------------------------------------------------------* DESCRIPTION:  (CHIP memory mapped register definitions)***\******************************************************************************//*-----------------------------------------------------------------------------------** Register Macros for TMR1:*------------------------------------------------------------------------------------*//*------------------------------------------------------------------------------** Register Macros for TMR1 TMMD1 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR1_TMMD1_GET()			_REG_GET(_TMR1_TMMD1_ADDR)#define _TMR1_TMMD1_SET(Val)			_REG_SET(_TMR1_TMMD1_ADDR, Val)#define _TMR1_TMMD1_AOI(AND,OR,INV)		_REG_AOI(_TMR1_TMMD1_ADDR,AND,OR,INV)#define _TMR1_TMMD1_FGET(Field)			_FIELD_GET(_TMR1_TMMD1_ADDR, _TMR1_TMMD1_##Field##)#define _TMR1_TMMD1_FSET(Field, Val)		_FIELD_SET(_TMR1_TMMD1_ADDR, _TMR1_TMMD1_##Field##, Val)#define _TMR1_TMMD1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_TMR1_TMMD1_ADDR, _TMR1_TMMD1_##Field##, AND, OR, INV)#define _TMR1_TMMD1_TEST_SHIFT		(2)#define _TMR1_TMMD1_TEST_MK(n)		(((Uint16)(n) & 0x003fu) << _TMR1_TMMD1_TEST_SHIFT)#define _TMR1_TMMD1_TEST_MASK			(_TMR1_TMMD1_TEST_MK(0x003fu))#define _TMR1_TMMD1_TEST_CLR			(~(_TMR1_TMMD1_TEST_MASK))#define _TMR1_TMMD1_MODE_SHIFT		(0)#define _TMR1_TMMD1_MODE_MK(n)		((Uint16)(n) & 0x0003u) #define _TMR1_TMMD1_MODE_MASK			(_TMR1_TMMD1_MODE_MK(0x0003u))#define _TMR1_TMMD1_MODE_CLR			(~(_TMR1_TMMD1_MODE_MASK))/*------------------------------------------------------------------------------** Register Macros for TMR1 TMRSV1 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR1_TMRSV1_GET()			_REG_GET(_TMR1_TMRSV1_ADDR)#define _TMR1_TMRSV1_SET(Val)			_REG_SET(_TMR1_TMRSV1_ADDR, Val)#define _TMR1_TMRSV1_AOI(AND,OR,INV)		_REG_AOI(_TMR1_TMRSV1_ADDR,AND,OR,INV)/*------------------------------------------------------------------------------** Register Macros for TMR1 TMPRSCL1 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR1_TMPRSCL1_GET()			_REG_GET(_TMR1_TMPRSCL1_ADDR)#define _TMR1_TMPRSCL1_SET(Val)			_REG_SET(_TMR1_TMPRSCL1_ADDR, Val)#define _TMR1_TMPRSCL1_AOI(AND,OR,INV)		_REG_AOI(_TMR1_TMPRSCL1_ADDR,AND,OR,INV)#define _TMR1_TMPRSCL1_FGET(Field)			_FIELD_GET(_TMR1_TMPRSCL1_ADDR, _TMR1_TMPRSCL1_##Field##)#define _TMR1_TMPRSCL1_FSET(Field, Val)		_FIELD_SET(_TMR1_TMPRSCL1_ADDR, _TMR1_TMPRSCL1_##Field##, Val)#define _TMR1_TMPRSCL1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_TMR1_TMPRSCL1_ADDR, _TMR1_TMPRSCL1_##Field##, AND, OR, INV)#define _TMR1_TMPRSCL1_PRSCL_SHIFT		(0)#define _TMR1_TMPRSCL1_PRSCL_MK(n)		((Uint16)(n) & 0x03ffu) #define _TMR1_TMPRSCL1_PRSCL_MASK			(_TMR1_TMPRSCL1_PRSCL_MK(0x03ffu))#define _TMR1_TMPRSCL1_PRSCL_CLR			(~(_TMR1_TMPRSCL1_PRSCL_MASK))/*------------------------------------------------------------------------------** Register Macros for TMR1 TMDIV1 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR1_TMDIV1_GET()			_REG_GET(_TMR1_TMDIV1_ADDR)#define _TMR1_TMDIV1_SET(Val)			_REG_SET(_TMR1_TMDIV1_ADDR, Val)#define _TMR1_TMDIV1_AOI(AND,OR,INV)		_REG_AOI(_TMR1_TMDIV1_ADDR,AND,OR,INV)/*------------------------------------------------------------------------------** Register Macros for TMR1 TMTRG1 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR1_TMTRG1_GET()			_REG_GET(_TMR1_TMTRG1_ADDR)#define _TMR1_TMTRG1_SET(Val)			_REG_SET(_TMR1_TMTRG1_ADDR, Val)#define _TMR1_TMTRG1_AOI(AND,OR,INV)		_REG_AOI(_TMR1_TMTRG1_ADDR,AND,OR,INV)#define _TMR1_TMTRG1_FGET(Field)			_FIELD_GET(_TMR1_TMTRG1_ADDR, _TMR1_TMTRG1_##Field##)#define _TMR1_TMTRG1_FSET(Field, Val)		_FIELD_SET(_TMR1_TMTRG1_ADDR, _TMR1_TMTRG1_##Field##, Val)#define _TMR1_TMTRG1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_TMR1_TMTRG1_ADDR, _TMR1_TMTRG1_##Field##, AND, OR, INV)#define _TMR1_TMTRG1_TRG_SHIFT		(0)#define _TMR1_TMTRG1_TRG_MK(n)		((Uint16)(n) & 0x0001u) #define _TMR1_TMTRG1_TRG_MASK			(_TMR1_TMTRG1_TRG_MK(0x0001u))#define _TMR1_TMTRG1_TRG_CLR			(~(_TMR1_TMTRG1_TRG_MASK))/*------------------------------------------------------------------------------** Register Macros for TMR1 TMCNT1 register :*                                                                                    *                                                                                    *                                                                                    *---------------------------------------------------------------------------------*/#define _TMR1_TMCNT1_GET()			_REG_GET(_TMR1_TMCNT1_ADDR)#define _TMR1_TMCNT1_SET(Val)			_REG_SET(_TMR1_TMCNT1_ADDR, Val)#define _TMR1_TMCNT1_AOI(AND,OR,INV)		_REG_AOI(_TMR1_TMCNT1_ADDR,AND,OR,INV)

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