📄 csl_emifhal_270.h
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* * *---------------------------------------------------------------------------------*/#define _EMIF_DMADEVSEL_GET() _REG_GET(_EMIF_DMADEVSEL_ADDR)#define _EMIF_DMADEVSEL_SET(Val) _REG_SET(_EMIF_DMADEVSEL_ADDR, Val)#define _EMIF_DMADEVSEL_AOI(AND,OR,INV) _REG_AOI(_EMIF_DMADEVSEL_ADDR,AND,OR,INV)#define _EMIF_DMADEVSEL_FGET(Field) _FIELD_GET(_EMIF_DMADEVSEL_ADDR, _EMIF_DMADEVSEL_##Field##)#define _EMIF_DMADEVSEL_FSET(Field, Val) _FIELD_SET(_EMIF_DMADEVSEL_ADDR, _EMIF_DMADEVSEL_##Field##, Val)#define _EMIF_DMADEVSEL_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DMADEVSEL_ADDR, _EMIF_DMADEVSEL_##Field##, AND, OR, INV)#define _EMIF_DMADEVSEL_SDV_SHIFT (4)#define _EMIF_DMADEVSEL_SDV_MK(n) (((Uint16)(n) & 0x0007u) << _EMIF_DMADEVSEL_SDV_SHIFT)#define _EMIF_DMADEVSEL_SDV_MASK (_EMIF_DMADEVSEL_SDV_MK(0x0007u))#define _EMIF_DMADEVSEL_SDV_CLR (~(_EMIF_DMADEVSEL_SDV_MASK))#define _EMIF_DMADEVSEL_DDV_SHIFT (0)#define _EMIF_DMADEVSEL_DDV_MK(n) ((Uint16)(n) & 0x0007u) #define _EMIF_DMADEVSEL_DDV_MASK (_EMIF_DMADEVSEL_DDV_MK(0x0007u))#define _EMIF_DMADEVSEL_DDV_CLR (~(_EMIF_DMADEVSEL_DDV_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF DMACTL register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DMACTL_GET() _REG_GET(_EMIF_DMACTL_ADDR)#define _EMIF_DMACTL_SET(Val) _REG_SET(_EMIF_DMACTL_ADDR, Val)#define _EMIF_DMACTL_AOI(AND,OR,INV) _REG_AOI(_EMIF_DMACTL_ADDR,AND,OR,INV)#define _EMIF_DMACTL_FGET(Field) _FIELD_GET(_EMIF_DMACTL_ADDR, _EMIF_DMACTL_##Field##)#define _EMIF_DMACTL_FSET(Field, Val) _FIELD_SET(_EMIF_DMACTL_ADDR, _EMIF_DMACTL_##Field##, Val)#define _EMIF_DMACTL_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DMACTL_ADDR, _EMIF_DMACTL_##Field##, AND, OR, INV)#define _EMIF_DMACTL_ENDI_SHIFT (8)#define _EMIF_DMACTL_ENDI_MK(n) (((Uint16)(n) & 0x0003u) << _EMIF_DMACTL_ENDI_SHIFT)#define _EMIF_DMACTL_ENDI_MASK (_EMIF_DMACTL_ENDI_MK(0x0003u))#define _EMIF_DMACTL_ENDI_CLR (~(_EMIF_DMACTL_ENDI_MASK))#define _EMIF_DMACTL_GO_SHIFT (0)#define _EMIF_DMACTL_GO_MK(n) ((Uint16)(n) & 0x0001u) #define _EMIF_DMACTL_GO_MASK (_EMIF_DMACTL_GO_MK(0x0001u))#define _EMIF_DMACTL_GO_CLR (~(_EMIF_DMACTL_GO_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF IMGDSPADDH register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_IMGDSPADDH_GET() _REG_GET(_EMIF_IMGDSPADDH_ADDR)#define _EMIF_IMGDSPADDH_SET(Val) _REG_SET(_EMIF_IMGDSPADDH_ADDR, Val)#define _EMIF_IMGDSPADDH_AOI(AND,OR,INV) _REG_AOI(_EMIF_IMGDSPADDH_ADDR,AND,OR,INV)#define _EMIF_IMGDSPADDH_FGET(Field) _FIELD_GET(_EMIF_IMGDSPADDH_ADDR, _EMIF_IMGDSPADDH_##Field##)#define _EMIF_IMGDSPADDH_FSET(Field, Val) _FIELD_SET(_EMIF_IMGDSPADDH_ADDR, _EMIF_IMGDSPADDH_##Field##, Val)#define _EMIF_IMGDSPADDH_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_IMGDSPADDH_ADDR, _EMIF_IMGDSPADDH_##Field##, AND, OR, INV)#define _EMIF_IMGDSPADDH_CDAH_SHIFT (0)#define _EMIF_IMGDSPADDH_CDAH_MK(n) ((Uint16)(n) & 0x007fu) #define _EMIF_IMGDSPADDH_CDAH_MASK (_EMIF_IMGDSPADDH_CDAH_MK(0x007fu))#define _EMIF_IMGDSPADDH_CDAH_CLR (~(_EMIF_IMGDSPADDH_CDAH_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF IMGDSPADDL register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_IMGDSPADDL_GET() _REG_GET(_EMIF_IMGDSPADDL_ADDR)#define _EMIF_IMGDSPADDL_SET(Val) _REG_SET(_EMIF_IMGDSPADDL_ADDR, Val)#define _EMIF_IMGDSPADDL_AOI(AND,OR,INV) _REG_AOI(_EMIF_IMGDSPADDL_ADDR,AND,OR,INV)/*------------------------------------------------------------------------------** Register Macros for EMIF DPSTR0 register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DPSTR0_GET() _REG_GET(_EMIF_DPSTR0_ADDR)#define _EMIF_DPSTR0_SET(Val) _REG_SET(_EMIF_DPSTR0_ADDR, Val)#define _EMIF_DPSTR0_AOI(AND,OR,INV) _REG_AOI(_EMIF_DPSTR0_ADDR,AND,OR,INV)#define _EMIF_DPSTR0_FGET(Field) _FIELD_GET(_EMIF_DPSTR0_ADDR, _EMIF_DPSTR0_##Field##)#define _EMIF_DPSTR0_FSET(Field, Val) _FIELD_SET(_EMIF_DPSTR0_ADDR, _EMIF_DPSTR0_##Field##, Val)#define _EMIF_DPSTR0_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DPSTR0_ADDR, _EMIF_DPSTR0_##Field##, AND, OR, INV)#define _EMIF_DPSTR0_DST0_SHIFT (0)#define _EMIF_DPSTR0_DST0_MK(n) ((Uint16)(n) & 0x00ffu) #define _EMIF_DPSTR0_DST0_MASK (_EMIF_DPSTR0_DST0_MK(0x00ffu))#define _EMIF_DPSTR0_DST0_CLR (~(_EMIF_DPSTR0_DST0_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF DPSTR1 register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DPSTR1_GET() _REG_GET(_EMIF_DPSTR1_ADDR)#define _EMIF_DPSTR1_SET(Val) _REG_SET(_EMIF_DPSTR1_ADDR, Val)#define _EMIF_DPSTR1_AOI(AND,OR,INV) _REG_AOI(_EMIF_DPSTR1_ADDR,AND,OR,INV)#define _EMIF_DPSTR1_FGET(Field) _FIELD_GET(_EMIF_DPSTR1_ADDR, _EMIF_DPSTR1_##Field##)#define _EMIF_DPSTR1_FSET(Field, Val) _FIELD_SET(_EMIF_DPSTR1_ADDR, _EMIF_DPSTR1_##Field##, Val)#define _EMIF_DPSTR1_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DPSTR1_ADDR, _EMIF_DPSTR1_##Field##, AND, OR, INV)#define _EMIF_DPSTR1_DST1_SHIFT (0)#define _EMIF_DPSTR1_DST1_MK(n) ((Uint16)(n) & 0x00ffu) #define _EMIF_DPSTR1_DST1_MASK (_EMIF_DPSTR1_DST1_MK(0x00ffu))#define _EMIF_DPSTR1_DST1_CLR (~(_EMIF_DPSTR1_DST1_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF DPSTR2 register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DPSTR2_GET() _REG_GET(_EMIF_DPSTR2_ADDR)#define _EMIF_DPSTR2_SET(Val) _REG_SET(_EMIF_DPSTR2_ADDR, Val)#define _EMIF_DPSTR2_AOI(AND,OR,INV) _REG_AOI(_EMIF_DPSTR2_ADDR,AND,OR,INV)#define _EMIF_DPSTR2_FGET(Field) _FIELD_GET(_EMIF_DPSTR2_ADDR, _EMIF_DPSTR2_##Field##)#define _EMIF_DPSTR2_FSET(Field, Val) _FIELD_SET(_EMIF_DPSTR2_ADDR, _EMIF_DPSTR2_##Field##, Val)#define _EMIF_DPSTR2_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DPSTR2_ADDR, _EMIF_DPSTR2_##Field##, AND, OR, INV)#define _EMIF_DPSTR2_DST2_SHIFT (0)#define _EMIF_DPSTR2_DST2_MK(n) ((Uint16)(n) & 0x00ffu) #define _EMIF_DPSTR2_DST2_MASK (_EMIF_DPSTR2_DST2_MK(0x00ffu))#define _EMIF_DPSTR2_DST2_CLR (~(_EMIF_DPSTR2_DST2_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF DPSTR3 register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DPSTR3_GET() _REG_GET(_EMIF_DPSTR3_ADDR)#define _EMIF_DPSTR3_SET(Val) _REG_SET(_EMIF_DPSTR3_ADDR, Val)#define _EMIF_DPSTR3_AOI(AND,OR,INV) _REG_AOI(_EMIF_DPSTR3_ADDR,AND,OR,INV)#define _EMIF_DPSTR3_FGET(Field) _FIELD_GET(_EMIF_DPSTR3_ADDR, _EMIF_DPSTR3_##Field##)#define _EMIF_DPSTR3_FSET(Field, Val) _FIELD_SET(_EMIF_DPSTR3_ADDR, _EMIF_DPSTR3_##Field##, Val)#define _EMIF_DPSTR3_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DPSTR3_ADDR, _EMIF_DPSTR3_##Field##, AND, OR, INV)#define _EMIF_DPSTR3_DST3_SHIFT (0)#define _EMIF_DPSTR3_DST3_MK(n) ((Uint16)(n) & 0x00ffu) #define _EMIF_DPSTR3_DST3_MASK (_EMIF_DPSTR3_DST3_MK(0x00ffu))#define _EMIF_DPSTR3_DST3_CLR (~(_EMIF_DPSTR3_DST3_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF DPSTR4 register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DPSTR4_GET() _REG_GET(_EMIF_DPSTR4_ADDR)#define _EMIF_DPSTR4_SET(Val) _REG_SET(_EMIF_DPSTR4_ADDR, Val)#define _EMIF_DPSTR4_AOI(AND,OR,INV) _REG_AOI(_EMIF_DPSTR4_ADDR,AND,OR,INV)#define _EMIF_DPSTR4_FGET(Field) _FIELD_GET(_EMIF_DPSTR4_ADDR, _EMIF_DPSTR4_##Field##)#define _EMIF_DPSTR4_FSET(Field, Val) _FIELD_SET(_EMIF_DPSTR4_ADDR, _EMIF_DPSTR4_##Field##, Val)#define _EMIF_DPSTR4_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DPSTR4_ADDR, _EMIF_DPSTR4_##Field##, AND, OR, INV)#define _EMIF_DPSTR4_DST4_SHIFT (0)#define _EMIF_DPSTR4_DST4_MK(n) ((Uint16)(n) & 0x00ffu) #define _EMIF_DPSTR4_DST4_MASK (_EMIF_DPSTR4_DST4_MK(0x00ffu))#define _EMIF_DPSTR4_DST4_CLR (~(_EMIF_DPSTR4_DST4_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF DPSTR5 register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_DPSTR5_GET() _REG_GET(_EMIF_DPSTR5_ADDR)#define _EMIF_DPSTR5_SET(Val) _REG_SET(_EMIF_DPSTR5_ADDR, Val)#define _EMIF_DPSTR5_AOI(AND,OR,INV) _REG_AOI(_EMIF_DPSTR5_ADDR,AND,OR,INV)#define _EMIF_DPSTR5_FGET(Field) _FIELD_GET(_EMIF_DPSTR5_ADDR, _EMIF_DPSTR5_##Field##)#define _EMIF_DPSTR5_FSET(Field, Val) _FIELD_SET(_EMIF_DPSTR5_ADDR, _EMIF_DPSTR5_##Field##, Val)#define _EMIF_DPSTR5_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_DPSTR5_ADDR, _EMIF_DPSTR5_##Field##, AND, OR, INV)#define _EMIF_DPSTR5_DST5_SHIFT (0)#define _EMIF_DPSTR5_DST5_MK(n) ((Uint16)(n) & 0x00ffu) #define _EMIF_DPSTR5_DST5_MASK (_EMIF_DPSTR5_DST5_MK(0x00ffu))#define _EMIF_DPSTR5_DST5_CLR (~(_EMIF_DPSTR5_DST5_MASK))/*------------------------------------------------------------------------------** Register Macros for EMIF TEST register :* * * *---------------------------------------------------------------------------------*/#define _EMIF_TEST_GET() _REG_GET(_EMIF_TEST_ADDR)#define _EMIF_TEST_SET(Val) _REG_SET(_EMIF_TEST_ADDR, Val)#define _EMIF_TEST_AOI(AND,OR,INV) _REG_AOI(_EMIF_TEST_ADDR,AND,OR,INV)#define _EMIF_TEST_FGET(Field) _FIELD_GET(_EMIF_TEST_ADDR, _EMIF_TEST_##Field##)#define _EMIF_TEST_FSET(Field, Val) _FIELD_SET(_EMIF_TEST_ADDR, _EMIF_TEST_##Field##, Val)#define _EMIF_TEST_FAOI(Field, AND, OR, INV) _FIELD_AOI(_EMIF_TEST_ADDR, _EMIF_TEST_##Field##, AND, OR, INV)#define _EMIF_TEST_TEST_SHIFT (0)#define _EMIF_TEST_TEST_MK(n) ((Uint16)(n) & 0x0001u) #define _EMIF_TEST_TEST_MASK (_EMIF_TEST_TEST_MK(0x0001u))#define _EMIF_TEST_TEST_CLR (~(_EMIF_TEST_TEST_MASK))⌨️ 快捷键说明
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