csl_emifhal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... EMIF - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_emifhal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for EMIF:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS0CTRL1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _EMIF_CS0CTRL1_GET()			_REG_GET(_EMIF_CS0CTRL1_ADDR)
#define _EMIF_CS0CTRL1_SET(Val)			_REG_SET(_EMIF_CS0CTRL1_ADDR, Val)
#define _EMIF_CS0CTRL1_AOI(AND,OR,INV)		_REG_AOI(_EMIF_CS0CTRL1_ADDR,AND,OR,INV)
#define _EMIF_CS0CTRL1_FGET(Field)			_FIELD_GET(_EMIF_CS0CTRL1_ADDR, _EMIF_CS0CTRL1_##Field##)
#define _EMIF_CS0CTRL1_FSET(Field, Val)		_FIELD_SET(_EMIF_CS0CTRL1_ADDR, _EMIF_CS0CTRL1_##Field##, Val)
#define _EMIF_CS0CTRL1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_EMIF_CS0CTRL1_ADDR, _EMIF_CS0CTRL1_##Field##, AND, OR, INV)

#define _EMIF_CS0CTRL1_OEC0_SHIFT		(12)
#define _EMIF_CS0CTRL1_OEC0_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS0CTRL1_OEC0_SHIFT)
#define _EMIF_CS0CTRL1_OEC0_MASK			(_EMIF_CS0CTRL1_OEC0_MK(0x000fu))
#define _EMIF_CS0CTRL1_OEC0_CLR			(~(_EMIF_CS0CTRL1_OEC0_MASK))

#define _EMIF_CS0CTRL1_WEC0_SHIFT		(8)
#define _EMIF_CS0CTRL1_WEC0_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS0CTRL1_WEC0_SHIFT)
#define _EMIF_CS0CTRL1_WEC0_MASK			(_EMIF_CS0CTRL1_WEC0_MK(0x000fu))
#define _EMIF_CS0CTRL1_WEC0_CLR			(~(_EMIF_CS0CTRL1_WEC0_MASK))

#define _EMIF_CS0CTRL1_CEC0_SHIFT		(4)
#define _EMIF_CS0CTRL1_CEC0_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS0CTRL1_CEC0_SHIFT)
#define _EMIF_CS0CTRL1_CEC0_MASK			(_EMIF_CS0CTRL1_CEC0_MK(0x000fu))
#define _EMIF_CS0CTRL1_CEC0_CLR			(~(_EMIF_CS0CTRL1_CEC0_MASK))

#define _EMIF_CS0CTRL1_CYCL0_SHIFT		(0)
#define _EMIF_CS0CTRL1_CYCL0_MK(n)		((Uint16)(n) & 0x000fu) 
#define _EMIF_CS0CTRL1_CYCL0_MASK			(_EMIF_CS0CTRL1_CYCL0_MK(0x000fu))
#define _EMIF_CS0CTRL1_CYCL0_CLR			(~(_EMIF_CS0CTRL1_CYCL0_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS0CTRL2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _EMIF_CS0CTRL2_GET()			_REG_GET(_EMIF_CS0CTRL2_ADDR)
#define _EMIF_CS0CTRL2_SET(Val)			_REG_SET(_EMIF_CS0CTRL2_ADDR, Val)
#define _EMIF_CS0CTRL2_AOI(AND,OR,INV)		_REG_AOI(_EMIF_CS0CTRL2_ADDR,AND,OR,INV)
#define _EMIF_CS0CTRL2_FGET(Field)			_FIELD_GET(_EMIF_CS0CTRL2_ADDR, _EMIF_CS0CTRL2_##Field##)
#define _EMIF_CS0CTRL2_FSET(Field, Val)		_FIELD_SET(_EMIF_CS0CTRL2_ADDR, _EMIF_CS0CTRL2_##Field##, Val)
#define _EMIF_CS0CTRL2_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_EMIF_CS0CTRL2_ADDR, _EMIF_CS0CTRL2_##Field##, AND, OR, INV)

#define _EMIF_CS0CTRL2_IDLE0_SHIFT		(12)
#define _EMIF_CS0CTRL2_IDLE0_MK(n)		(((Uint16)(n) & 0x0003u) << _EMIF_CS0CTRL2_IDLE0_SHIFT)
#define _EMIF_CS0CTRL2_IDLE0_MASK			(_EMIF_CS0CTRL2_IDLE0_MK(0x0003u))
#define _EMIF_CS0CTRL2_IDLE0_CLR			(~(_EMIF_CS0CTRL2_IDLE0_MASK))

#define _EMIF_CS0CTRL2_OESU0_SHIFT		(8)
#define _EMIF_CS0CTRL2_OESU0_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS0CTRL2_OESU0_SHIFT)
#define _EMIF_CS0CTRL2_OESU0_MASK			(_EMIF_CS0CTRL2_OESU0_MK(0x000fu))
#define _EMIF_CS0CTRL2_OESU0_CLR			(~(_EMIF_CS0CTRL2_OESU0_MASK))

#define _EMIF_CS0CTRL2_WESU0_SHIFT		(4)
#define _EMIF_CS0CTRL2_WESU0_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS0CTRL2_WESU0_SHIFT)
#define _EMIF_CS0CTRL2_WESU0_MASK			(_EMIF_CS0CTRL2_WESU0_MK(0x000fu))
#define _EMIF_CS0CTRL2_WESU0_CLR			(~(_EMIF_CS0CTRL2_WESU0_MASK))

#define _EMIF_CS0CTRL2_CESU0_SHIFT		(0)
#define _EMIF_CS0CTRL2_CESU0_MK(n)		((Uint16)(n) & 0x000fu) 
#define _EMIF_CS0CTRL2_CESU0_MASK			(_EMIF_CS0CTRL2_CESU0_MK(0x000fu))
#define _EMIF_CS0CTRL2_CESU0_CLR			(~(_EMIF_CS0CTRL2_CESU0_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS1CTRL1A register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _EMIF_CS1CTRL1A_GET()			_REG_GET(_EMIF_CS1CTRL1A_ADDR)
#define _EMIF_CS1CTRL1A_SET(Val)			_REG_SET(_EMIF_CS1CTRL1A_ADDR, Val)
#define _EMIF_CS1CTRL1A_AOI(AND,OR,INV)		_REG_AOI(_EMIF_CS1CTRL1A_ADDR,AND,OR,INV)
#define _EMIF_CS1CTRL1A_FGET(Field)			_FIELD_GET(_EMIF_CS1CTRL1A_ADDR, _EMIF_CS1CTRL1A_##Field##)
#define _EMIF_CS1CTRL1A_FSET(Field, Val)		_FIELD_SET(_EMIF_CS1CTRL1A_ADDR, _EMIF_CS1CTRL1A_##Field##, Val)
#define _EMIF_CS1CTRL1A_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_EMIF_CS1CTRL1A_ADDR, _EMIF_CS1CTRL1A_##Field##, AND, OR, INV)

#define _EMIF_CS1CTRL1A_CEC1_SHIFT		(8)
#define _EMIF_CS1CTRL1A_CEC1_MK(n)		(((Uint16)(n) & 0x001fu) << _EMIF_CS1CTRL1A_CEC1_SHIFT)
#define _EMIF_CS1CTRL1A_CEC1_MASK			(_EMIF_CS1CTRL1A_CEC1_MK(0x001fu))
#define _EMIF_CS1CTRL1A_CEC1_CLR			(~(_EMIF_CS1CTRL1A_CEC1_MASK))

#define _EMIF_CS1CTRL1A_CYCL1_SHIFT		(0)
#define _EMIF_CS1CTRL1A_CYCL1_MK(n)		((Uint16)(n) & 0x001fu) 
#define _EMIF_CS1CTRL1A_CYCL1_MASK			(_EMIF_CS1CTRL1A_CYCL1_MK(0x001fu))
#define _EMIF_CS1CTRL1A_CYCL1_CLR			(~(_EMIF_CS1CTRL1A_CYCL1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS1CTRL1B register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _EMIF_CS1CTRL1B_GET()			_REG_GET(_EMIF_CS1CTRL1B_ADDR)
#define _EMIF_CS1CTRL1B_SET(Val)			_REG_SET(_EMIF_CS1CTRL1B_ADDR, Val)
#define _EMIF_CS1CTRL1B_AOI(AND,OR,INV)		_REG_AOI(_EMIF_CS1CTRL1B_ADDR,AND,OR,INV)
#define _EMIF_CS1CTRL1B_FGET(Field)			_FIELD_GET(_EMIF_CS1CTRL1B_ADDR, _EMIF_CS1CTRL1B_##Field##)
#define _EMIF_CS1CTRL1B_FSET(Field, Val)		_FIELD_SET(_EMIF_CS1CTRL1B_ADDR, _EMIF_CS1CTRL1B_##Field##, Val)
#define _EMIF_CS1CTRL1B_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_EMIF_CS1CTRL1B_ADDR, _EMIF_CS1CTRL1B_##Field##, AND, OR, INV)

#define _EMIF_CS1CTRL1B_OEC1_SHIFT		(8)
#define _EMIF_CS1CTRL1B_OEC1_MK(n)		(((Uint16)(n) & 0x001fu) << _EMIF_CS1CTRL1B_OEC1_SHIFT)
#define _EMIF_CS1CTRL1B_OEC1_MASK			(_EMIF_CS1CTRL1B_OEC1_MK(0x001fu))
#define _EMIF_CS1CTRL1B_OEC1_CLR			(~(_EMIF_CS1CTRL1B_OEC1_MASK))

#define _EMIF_CS1CTRL1B_WEC1_SHIFT		(0)
#define _EMIF_CS1CTRL1B_WEC1_MK(n)		((Uint16)(n) & 0x001fu) 
#define _EMIF_CS1CTRL1B_WEC1_MASK			(_EMIF_CS1CTRL1B_WEC1_MK(0x001fu))
#define _EMIF_CS1CTRL1B_WEC1_CLR			(~(_EMIF_CS1CTRL1B_WEC1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS1CTRL2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _EMIF_CS1CTRL2_GET()			_REG_GET(_EMIF_CS1CTRL2_ADDR)
#define _EMIF_CS1CTRL2_SET(Val)			_REG_SET(_EMIF_CS1CTRL2_ADDR, Val)
#define _EMIF_CS1CTRL2_AOI(AND,OR,INV)		_REG_AOI(_EMIF_CS1CTRL2_ADDR,AND,OR,INV)
#define _EMIF_CS1CTRL2_FGET(Field)			_FIELD_GET(_EMIF_CS1CTRL2_ADDR, _EMIF_CS1CTRL2_##Field##)
#define _EMIF_CS1CTRL2_FSET(Field, Val)		_FIELD_SET(_EMIF_CS1CTRL2_ADDR, _EMIF_CS1CTRL2_##Field##, Val)
#define _EMIF_CS1CTRL2_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_EMIF_CS1CTRL2_ADDR, _EMIF_CS1CTRL2_##Field##, AND, OR, INV)

#define _EMIF_CS1CTRL2_IDLE1_SHIFT		(12)
#define _EMIF_CS1CTRL2_IDLE1_MK(n)		(((Uint16)(n) & 0x0003u) << _EMIF_CS1CTRL2_IDLE1_SHIFT)
#define _EMIF_CS1CTRL2_IDLE1_MASK			(_EMIF_CS1CTRL2_IDLE1_MK(0x0003u))
#define _EMIF_CS1CTRL2_IDLE1_CLR			(~(_EMIF_CS1CTRL2_IDLE1_MASK))

#define _EMIF_CS1CTRL2_OESU1_SHIFT		(8)
#define _EMIF_CS1CTRL2_OESU1_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS1CTRL2_OESU1_SHIFT)
#define _EMIF_CS1CTRL2_OESU1_MASK			(_EMIF_CS1CTRL2_OESU1_MK(0x000fu))
#define _EMIF_CS1CTRL2_OESU1_CLR			(~(_EMIF_CS1CTRL2_OESU1_MASK))

#define _EMIF_CS1CTRL2_WESU1_SHIFT		(4)
#define _EMIF_CS1CTRL2_WESU1_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS1CTRL2_WESU1_SHIFT)
#define _EMIF_CS1CTRL2_WESU1_MASK			(_EMIF_CS1CTRL2_WESU1_MK(0x000fu))
#define _EMIF_CS1CTRL2_WESU1_CLR			(~(_EMIF_CS1CTRL2_WESU1_MASK))

#define _EMIF_CS1CTRL2_CESU1_SHIFT		(0)
#define _EMIF_CS1CTRL2_CESU1_MK(n)		((Uint16)(n) & 0x000fu) 
#define _EMIF_CS1CTRL2_CESU1_MASK			(_EMIF_CS1CTRL2_CESU1_MK(0x000fu))
#define _EMIF_CS1CTRL2_CESU1_CLR			(~(_EMIF_CS1CTRL2_CESU1_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS2CTRL1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _EMIF_CS2CTRL1_GET()			_REG_GET(_EMIF_CS2CTRL1_ADDR)
#define _EMIF_CS2CTRL1_SET(Val)			_REG_SET(_EMIF_CS2CTRL1_ADDR, Val)
#define _EMIF_CS2CTRL1_AOI(AND,OR,INV)		_REG_AOI(_EMIF_CS2CTRL1_ADDR,AND,OR,INV)
#define _EMIF_CS2CTRL1_FGET(Field)			_FIELD_GET(_EMIF_CS2CTRL1_ADDR, _EMIF_CS2CTRL1_##Field##)
#define _EMIF_CS2CTRL1_FSET(Field, Val)		_FIELD_SET(_EMIF_CS2CTRL1_ADDR, _EMIF_CS2CTRL1_##Field##, Val)
#define _EMIF_CS2CTRL1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_EMIF_CS2CTRL1_ADDR, _EMIF_CS2CTRL1_##Field##, AND, OR, INV)

#define _EMIF_CS2CTRL1_OEC2_SHIFT		(12)
#define _EMIF_CS2CTRL1_OEC2_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS2CTRL1_OEC2_SHIFT)
#define _EMIF_CS2CTRL1_OEC2_MASK			(_EMIF_CS2CTRL1_OEC2_MK(0x000fu))
#define _EMIF_CS2CTRL1_OEC2_CLR			(~(_EMIF_CS2CTRL1_OEC2_MASK))

#define _EMIF_CS2CTRL1_WEC2_SHIFT		(8)
#define _EMIF_CS2CTRL1_WEC2_MK(n)		(((Uint16)(n) & 0x000fu) << _EMIF_CS2CTRL1_WEC2_SHIFT)
#define _EMIF_CS2CTRL1_WEC2_MASK			(_EMIF_CS2CTRL1_WEC2_MK(0x000fu))
#define _EMIF_CS2CTRL1_WEC2_CLR			(~(_EMIF_CS2CTRL1_WEC2_MASK))

#define _EMIF_CS2CTRL1_CYCL2_SHIFT		(0)
#define _EMIF_CS2CTRL1_CYCL2_MK(n)		((Uint16)(n) & 0x000fu) 
#define _EMIF_CS2CTRL1_CYCL2_MASK			(_EMIF_CS2CTRL1_CYCL2_MK(0x000fu))
#define _EMIF_CS2CTRL1_CYCL2_CLR			(~(_EMIF_CS2CTRL1_CYCL2_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for EMIF CS2CTRL2 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/